]> git.the-white-hart.net Git - vhdl/shortlog
vhdl
2025-10-10 rsAdd divmod routine and test within emulator
2025-10-10 rsAdd binary artifiacts to .gitignore
2025-10-10 rsAdd vim swp files to .gitignore
2025-10-10 rsCommit progress on vga_console
2025-10-10 rsAdd emulator with mul_uu test
2025-10-10 rsUse local labels and fix duplicated label
2025-10-10 rsAdd local labels and error on label redefinition
2025-10-07 RyanAdd PS2 keyboard handling and remove old source
2025-10-04 rsAdd multi-file assembly project
2025-10-04 rsAdd clarifying comment to assembler
2025-10-04 rsUpdate CPU0 assembler
2025-10-04 rsFix PS2 interface interrupt and error flags
2025-10-03 RyanFix color-during-blank bug in vga tiler
2025-10-03 RyanAdjust VGA vert timing and change sync polarity
2025-10-02 RyanAdd VGA console print and memory subroutines
2025-10-02 rsAdd map file to .gitignore
2025-10-02 rsAdd IO test assembly program for CPU0
2025-10-02 rsFix step and run bugs in jtag debugger
2025-10-02 rsAdd mapfile generation to CPU0 assembler
2025-10-02 rsClean up unused signals in UART
2025-10-02 rsUpdate Wishbone debug entity
2025-09-30 RyanAdd arguments to jtag debug utility
2025-09-30 RyanSwitch full-system sim test to latest CPU0
2025-09-30 RyanAdd sparse array to simulated RAM
2025-09-30 RyanSwap file endianness to little for simulated flash
2025-09-30 RyanAdd JTAG debugging to CPU0
2025-09-30 RyanDrive Wishbone bridge with state machine
2025-09-30 RyanAdd default output reg value to jtag for sims
2025-09-30 RyanAdd missing signal to sensitivity list
2025-09-29 RyanAdd JTAG USERn registers and test to utility lib
2025-09-29 RyanRemove old test programs
2025-09-26 RyanAdd autoerase to digdude
2025-09-26 RyanAdd shift instructions to CPU0
2025-09-26 RyanFix whitespace
2025-09-25 rsAdd performance testing experiment
2025-09-25 rsAdd lil experiments, as a treat
2025-09-23 RyanAdd clock-optimized version of CPU0 project
2025-09-23 RyanRemove debug signals from CPU0 project
2025-09-23 RyanAdd Wisbhone register bridge
2025-09-21 rsAdd attempt at resource-optimized CPU
2025-09-19 rsAdd updated host controller
2025-09-19 rsAdd host regs with SRL clock divider
2025-09-19 rsAdd clock enable to seven-seg-mux
2025-09-18 RyanRemove default test data from VGA screen buffer
2025-09-18 RyanUse SRLs for watchdog timer in PS2 controler
2025-09-18 RyanUpdate for optimized version of CPU0 project
2025-09-18 RyanCreate copy of PS2 host for optimization
2025-09-17 RyanUpdate hardware test for nexys2 memctrl
2025-09-17 RyanUpdate ps2 tests to point at renamed entities
2025-09-17 RyanOrganize utility library
2025-09-17 RyanOrganize simulation library
2025-09-17 RyanRemove deprecated entities
2025-09-17 RyanRemove deprecated sim_memory
2025-09-17 RyanUpdate UART hardware test and baud rate comment
2025-09-17 RyanUpdate with lots of work, need to organize
2025-08-28 rsAdd RO simulated flash and simulation utilities
2025-08-23 rsRemove debug print
2025-07-03 rsAdd scripts to single-step cpu from host
2025-07-03 rsUpdate test programs
2025-07-03 rsUpdate project
2025-07-03 rsAdd align assembler directive
2025-06-29 rsSeparate CYC for flash and ram in mem controller
2025-06-29 rsMove power-on-reset into host_ctrl
2025-06-29 rsAdd new Wishbone address mapper
2025-06-29 rsUpdate cpu0 test programs
2025-06-29 rsRemove trailing whitespace
2025-06-28 rsAdd Wishbone docs to cpu and remove debug signals
2025-06-28 rsAdd documentation to VGA interface
2025-06-28 rsAdd Wishbone datasheet to RS232 UART
2025-06-28 rsAdd more documentation for PS2 and RS232 ifaces
2025-06-28 rsAdd documentation in nexys2 library
2025-06-28 rsAdd license
2025-06-28 rsInitial commit