From f7dd63c40c40469e36612ea3ed60ea8b1f077176 Mon Sep 17 00:00:00 2001
From: rs <>
Date: Fri, 12 Dec 2025 22:41:25 -0600
Subject: [PATCH] Update enable logic and add reset to pipectrl

---
 libraries/dsp/pipectrl.vhd            | 8 +++++---
 libraries/dsp/pipectrl_runout.vhd     | 4 ++--
 libraries/dsp/pipectrl_runout_srl.vhd | 6 ++----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index 39b55e4..c44b89e 100644
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -34,8 +34,8 @@ begin
 	-- Enable the stage register to latch if:
 	-- * it is currently empty
 	-- * if the downstream stage is accepting the current data
-	enable <= (not stb_reg) or rdy_i;
-	en_o   <= enable and stb_i;
+	enable <= ((not stb_reg) or rdy_i) and stb_i and (not rst_i);
+	en_o   <= enable;
 
 	stb_o <= stb_reg;
 	rdy_o <= enable;
@@ -55,7 +55,9 @@ begin
 	process (clk_i, enable, dat_i)
 	begin
 		if rising_edge(clk_i) then
-			if enable = '1' then
+			if rst_i = '1' then
+				dat_reg <= (others => '0');
+			elsif enable = '1' then
 				dat_reg <= dat_i;
 			end if;
 		end if;
diff --git a/libraries/dsp/pipectrl_runout.vhd b/libraries/dsp/pipectrl_runout.vhd
index 2e9b7fd..80650d5 100644
--- a/libraries/dsp/pipectrl_runout.vhd
+++ b/libraries/dsp/pipectrl_runout.vhd
@@ -45,8 +45,8 @@ begin
 	rdy_o <= rdy_reg;
 	dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
-	en      <= rdy_reg;
-	en_o    <= en and stb_i;
+	en      <= rdy_reg and stb_i and (not rst_i);
+	en_o    <= en;
 	rob_en  <= rdy_reg and (not rdy_i);
 	rob_clr <= rdy_i;
 
diff --git a/libraries/dsp/pipectrl_runout_srl.vhd b/libraries/dsp/pipectrl_runout_srl.vhd
index 301d2f0..a9015e9 100644
--- a/libraries/dsp/pipectrl_runout_srl.vhd
+++ b/libraries/dsp/pipectrl_runout_srl.vhd
@@ -34,13 +34,11 @@ architecture behavioral of pipectrl_runout_srl is
 	-- Normal interstage register
 	signal en:          std_logic;
 	signal stb_reg:     std_logic := '0';
-	--signal dat_reg:     std_logic_vector(WIDTH-1 downto 0);
 
 	-- Run-out-buffer
 	signal rob_en:      std_logic;
 	signal rob_clr:     std_logic;
 	signal rob_stb_reg: std_logic := '0';
-	--signal rob_dat_reg: std_logic_vector(WIDTH-1 downto 0);
 
 begin
 
@@ -48,8 +46,8 @@ begin
 	rdy_o <= rdy_reg;
 	--dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
-	en      <= rdy_reg;
-	en_o    <= en and stb_i;
+	en      <= rdy_reg and stb_i and (not rst_i);
+	en_o    <= en;
 	rob_en  <= rdy_reg and (not rdy_i);
 	rob_clr <= rdy_i;
 
-- 
2.43.0