From e6bc4afbeb43f24d763a1f2177bd4ffcf4b71c32 Mon Sep 17 00:00:00 2001
From: rs <>
Date: Sat, 28 Jun 2025 00:18:29 -0500
Subject: [PATCH] Add Wishbone datasheet to RS232 UART

---
 libraries/rs232/rs232_uart.vhd | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/libraries/rs232/rs232_uart.vhd b/libraries/rs232/rs232_uart.vhd
index 69ce1a3..04c6c75 100644
--- a/libraries/rs232/rs232_uart.vhd
+++ b/libraries/rs232/rs232_uart.vhd
@@ -74,6 +74,26 @@
 -- TODO: Detect and generate break conditions
 -- TODO: Add framing checks
 --------------------------------------------------------------------------------
+-- WISHBONE DATASHEET
+--
+-- Wishbone specification used: Rev B.3
+-- Interface type: device
+-- Port size: 8-bit
+-- Operand sizes: 8-bit
+-- Endianness: undefined (port size same as granularity)
+-- Data transfer sequence: undefined
+-- Clock constraints: none
+-- Signals:
+-- * rst_i
+-- * clk_i
+-- * cyc_i
+-- * stb_i
+-- * we_i
+-- * ack_o
+-- * adr_i (3-bit)
+-- * dat_i (8-bit)
+-- * dat_o (8-bit)
+--------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
-- 
2.43.0