From b7309341a4796ce6742ebea18e05cfd443edf29b Mon Sep 17 00:00:00 2001
From: rs <>
Date: Thu, 11 Dec 2025 21:09:24 -0600
Subject: [PATCH] Allow interstage register of zero width

---
 libraries/dsp/pipectrl.vhd | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index cde4634..39b55e4 100644
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -4,7 +4,7 @@ use ieee.std_logic_1164.all;
 
 entity pipectrl is
 	generic (
-		WIDTH: positive := 16
+		WIDTH: natural := 16
 	);
 	port (
 		rst_i: in  std_logic;
@@ -14,7 +14,7 @@ entity pipectrl is
 
 		stb_i: in  std_logic;
 		rdy_o: out std_logic;
-		dat_i: in  std_logic_vector(WIDTH-1 downto 0);
+		dat_i: in  std_logic_vector(WIDTH-1 downto 0) := (others => '0');
 
 		stb_o: out std_logic;
 		rdy_i: in  std_logic;
-- 
2.43.0