From a33bbada89a03b5e99e0d434277e8537dfe9bf6e Mon Sep 17 00:00:00 2001
From: rs <>
Date: Sat, 28 Jun 2025 00:42:31 -0500
Subject: [PATCH] Add Wishbone docs to cpu and remove debug signals

---
 projects/cpu_0/cpu.vhd    | 45 +++++++++++++++++++--------------------
 projects/cpu_0/nexys2.vhd | 12 +++--------
 2 files changed, 25 insertions(+), 32 deletions(-)

diff --git a/projects/cpu_0/cpu.vhd b/projects/cpu_0/cpu.vhd
index e283b24..d7dde24 100644
--- a/projects/cpu_0/cpu.vhd
+++ b/projects/cpu_0/cpu.vhd
@@ -8,6 +8,26 @@
 --    :   :
 --
 --------------------------------------------------------------------------------
+-- WISHBONE DATASHEET
+--
+-- Wishbone specification used: Rev B.3
+-- Interface type: master
+-- Port size: 8-bit
+-- Operand sizes: 8-bit, 32-bit
+-- Endianness: little
+-- Data transfer sequence: undefined
+-- Clock constraints: none
+-- Signals:
+-- * rst_i
+-- * clk_i
+-- * cyc_o
+-- * stb_o
+-- * we_o
+-- * ack_i
+-- * adr_o (32-bit)
+-- * dat_i (8-bit)
+-- * dat_o (8-bit)
+--------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -32,10 +52,7 @@ entity cpu is
 		dat_i: in  std_logic_vector(7 downto 0);
 
 		int_i: in  std_logic;
-		vec_i: in  std_logic_vector(7 downto 0);
-
-		debug_i: in  std_logic_vector(63 downto 0);
-		debug_o: out std_logic_vector(63 downto 0)
+		vec_i: in  std_logic_vector(7 downto 0)
 	);
 end cpu;
 
@@ -43,7 +60,6 @@ end cpu;
 architecture behavioral of cpu is
 
 	type state_t is (
-		S_WAIT,  S_FETCH_2,
 		S_RESET, S_FETCH, S_MEMORY,
 		S_IMM8,  S_IMM32_0, S_IMM32_1, S_IMM32_2, S_IMM32_3,
 		S_LD8,   S_LD32_0,  S_LD32_1,  S_LD32_2,  S_LD32_3,
@@ -137,8 +153,6 @@ architecture behavioral of cpu is
 	signal p:          std_logic;
 	signal ins_pc_sel: pc_sel_t;
 
-	signal debug_reg:  std_logic_vector(15 downto 0);
-
 begin
 
 	-- Control state machine
@@ -153,12 +167,7 @@ begin
 		end if;
 	end process;
 
-	debug_o(63 downto 32) <= pc_reg;
-	debug_o(15 downto  8) <= dat_i;
-	debug_o(23 downto 16) <= mdr_reg(7 downto 0);
-	debug_o( 7 downto  0) <= ins_reg;
-
-	process (state_reg, ack_i, ins_decode, int_i, ins_pc_sel, imask_reg, debug_i)
+	process (state_reg, ack_i, ins_decode, int_i, ins_pc_sel, imask_reg)
 	begin
 		state_next <= state_reg;
 		cyc_o      <= '0';
@@ -186,16 +195,6 @@ begin
 
 		case state_reg is
 			when S_FETCH =>
-				if debug_i(0) = '1' then
-					state_next <= S_WAIT;
-				end if;
-
-			when S_WAIT =>
-				if debug_i(0) = '0' then
-					state_next <= S_FETCH_2;
-				end if;
-
-			when S_FETCH_2 =>
 				adr_sel <= ADR_PC;
 				cyc_o   <= '1';
 				stb_o   <= '1';
diff --git a/projects/cpu_0/nexys2.vhd b/projects/cpu_0/nexys2.vhd
index c2f156d..24662fe 100644
--- a/projects/cpu_0/nexys2.vhd
+++ b/projects/cpu_0/nexys2.vhd
@@ -165,9 +165,6 @@ architecture behavioral of nexys2 is
 	signal int_vec:           std_logic_vector(7 downto 0);
 	signal ints:              std_logic_vector(15 downto 0);
 
-	signal debug_i:           std_logic_vector(63 downto 0);
-	signal debug_o:           std_logic_vector(63 downto 0);
-
 begin
 
 	Led <= mem_miso;
@@ -185,10 +182,7 @@ begin
 			dat_i => dat_miso,
 
 			int_i => int_cpu,
-			vec_i => int_vec,
-
-			debug_i => debug_o,
-			debug_o => debug_i
+			vec_i => int_vec
 		);
 
 	int_vec(7 downto 4) <= (others => '0');
@@ -387,8 +381,8 @@ begin
 			-- Signals to the internal device
 			d_rst_o      => h_rst,
 			d_flags_o    => host_flags,
-			debug_i      => debug_i,
-			debug_o      => debug_o,
+			debug_i      => (others => '0'),
+			debug_o      => open,
 
 			-- Internal access to control registers
 			d_cyc_i      => host_cyc,
-- 
2.43.0