From a0bfa8222809214380a5f0ea31f390991eb1db1f Mon Sep 17 00:00:00 2001 From: rs <> Date: Thu, 25 Sep 2025 00:00:04 -0500 Subject: [PATCH] Add lil experiments, as a treat --- projects/experimental/counters.vhd | 206 ++++++++++++++++++ projects/experimental/reset_priority.vhd | 152 +++++++++++++ projects/experimental/srl.vhd | 57 +++++ .../tests/test_srl_experiment.vhd | 39 ++++ 4 files changed, 454 insertions(+) create mode 100644 projects/experimental/counters.vhd create mode 100644 projects/experimental/reset_priority.vhd create mode 100644 projects/experimental/srl.vhd create mode 100644 projects/experimental/tests/test_srl_experiment.vhd diff --git a/projects/experimental/counters.vhd b/projects/experimental/counters.vhd new file mode 100644 index 0000000..90e3575 --- /dev/null +++ b/projects/experimental/counters.vhd @@ -0,0 +1,206 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; +use ieee.numeric_std.all; + + +entity counters is + port ( + rst: in std_logic; + clk: in std_logic; + en: in std_logic; + den: in std_logic; + + count: out std_logic_vector(15 downto 0); + target: in std_logic_vector(15 downto 0); + donezo: out std_logic + ); +end counters; + + +architecture behavioral of counters is + + signal count_reg: std_logic_vector(15 downto 0); + signal done: std_logic; + +begin + + -- Up-counter with enable and reset + -- Slices: 8 + -- Registers: 16 + -- Logic LUTs: 1 + -- Route-thru: 15 + --process (rst, clk, en, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif en = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + + -- Up-counter with no enable or reset, same resource usage + -- Slices: 8 + -- Registers: 16 + -- Logic LUTs: 1 + -- Route-thru: 15 + --process (clk, count_reg) + --begin + -- if rising_edge(clk) then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- end if; + --end process; + --count <= count_reg; + + -- Down-counter, logic and route-thru luts swap! + -- Slices: 8 + -- Registers: 16 + -- Logic LUTs: 15 + -- Route-thru: 1 + --process (clk, count_reg) + --begin + -- if rising_edge(clk) then + -- count_reg <= std_logic_vector(unsigned(count_reg) - 1); + -- end if; + --end process; + --count <= count_reg; + + -- Up-down-counter, one extra LUT used + -- Slices: 9 + -- Registers: 16 + -- Logic LUTs: 17 + -- Route-thru: 0 + --process (rst, clk, en, den, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif en = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- elsif den = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) - 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + + -- Up-down-counter inverted priority, same resources + -- Slices: 9 + -- Registers: 16 + -- Logic LUTs: 17 + -- Route-thru: 0 + --process (rst, clk, en, den, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif den = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) - 1); + -- elsif en = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + + -- Up-down-counter NOP on up+down, one extra LUT + -- Slices: 9 + -- Registers: 16 + -- Logic LUTs: 18 + -- Route-thru: 0 + --process (rst, clk, en, den, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif den = '0' and en = '1' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- elsif den = '1' and en = '0' then + -- count_reg <= std_logic_vector(unsigned(count_reg) - 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + + -- Up-counter match on constant value + -- Slices: 12 + -- Registers: 16 + -- Logic LUTs: 7 + -- Route-thru: 15 + --process (rst, clk, done, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif done = '0' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + --done <= '1' when count_reg = x"beef" else '0'; + --donezo <= done; + + -- Up-counter match on variable value + -- Slices: 12 + -- Registers: 16 + -- Logic LUTs: 9 + -- Route-thru: 15 + --process (rst, clk, done, count_reg) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= (others => '0'); + -- elsif done = '0' then + -- count_reg <= std_logic_vector(unsigned(count_reg) + 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + --done <= '1' when count_reg = target else '0'; + --donezo <= done; + + -- Down-counter load variable match on zero, one extra lut when or_reduce used? + -- Slices: 13 + -- Registers: 16 + -- Logic LUTs: 22 + -- Route-thru: 0 + --process (rst, clk, done, count_reg, target) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- count_reg <= target; + -- elsif done = '0' then + -- count_reg <= std_logic_vector(unsigned(count_reg) - 1); + -- end if; + -- end if; + --end process; + --count <= count_reg; + ----done <= not or_reduce(count_reg); + --done <= '1' when count_reg = x"0000" else '0'; + --donezo <= done; + + -- Down-counter load constant mach on zero + -- Slices: 12 + -- Registers: 16 + -- Logic LUTs: 21 + -- Route-thru: 1 + process (rst, clk, done, count_reg, target) + begin + if rising_edge(clk) then + if rst = '1' then + count_reg <= x"beef"; + elsif done = '0' then + count_reg <= std_logic_vector(unsigned(count_reg) - 1); + end if; + end if; + end process; + count <= count_reg; + done <= nor_reduce(count_reg); + --done <= '1' when count_reg = x"0000" else '0'; + donezo <= done; + +end behavioral; diff --git a/projects/experimental/reset_priority.vhd b/projects/experimental/reset_priority.vhd new file mode 100644 index 0000000..e04c679 --- /dev/null +++ b/projects/experimental/reset_priority.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity reset_priority is + port ( + clk: in std_logic; + rst: in std_logic; + set: in std_logic; + clr: in std_logic; + en: in std_logic; + + a: in std_logic; + b: in std_logic; + c: in std_logic; + d: in std_logic; + + q: out std_logic; + + aw: in std_logic_vector(15 downto 0); + bw: in std_logic_vector(15 downto 0); + cw: in std_logic_vector(15 downto 0); + dw: in std_logic_vector(15 downto 0); + + qw: out std_logic_vector(15 downto 0) + ); +end reset_priority; + + +architecture behavioral of reset_priority is + + signal x: std_logic; + +begin + + -- LUTs: 2 + --process (clk, rst, set, a, b, c, d) + --begin + -- if rst = '1' then + -- q <= '0'; + -- elsif rising_edge(clk) then + -- if set = '1' then + -- q <= '1'; + -- else + -- q <= a and b and c and d; + -- end if; + -- end if; + --end process; + + -- LUTs: 1 + --process (clk, rst, set, a, b, c, d) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- q <= '0'; + -- elsif set = '1' then + -- q <= '1'; + -- else + -- q <= a and b and c and d; + -- end if; + -- end if; + --end process; + + -- LUTs: 2 + --process (clk, rst, set, a, b, c, d) + --begin + -- if rising_edge(clk) then + -- if set = '1' then + -- q <= '1'; + -- elsif rst = '1' then + -- q <= '0'; + -- else + -- q <= a and b and c and d; + -- end if; + -- end if; + --end process; + + -- LUTs: 2 + --process (clk, rst, set, en, a, b, c, d) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- q <= '0'; + -- elsif en = '1' then + -- if set = '1' then + -- q <= '1'; + -- else + -- q <= a and b and c and d; + -- end if; + -- end if; + -- end if; + --end process; + + -- LUTs: 1 + --process (clk, rst, set, en, a, b, c, d) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- q <= '0'; + -- elsif set = '1' then + -- q <= '1'; + -- elsif en = '1' then + -- q <= a and b and c and d; + -- end if; + -- end if; + --end process; + + -- LUTs: 1 + --process (clk, rst, set, en, a, b, c, d) + --begin + -- if falling_edge(clk) then + -- if rst = '0' then + -- q <= '0'; + -- elsif set = '0' then + -- q <= '1'; + -- elsif en = '0' then + -- q <= a and b and c and d; + -- end if; + -- end if; + --end process; + + -- LUTs: 1 + --process (clk, rst, set, en, x) + --begin + -- if rising_edge(clk) then + -- if rst = '1' then + -- x <= '0'; + -- elsif set = '1' then + -- x <= '1'; + -- elsif en = '1' then + -- x <= not x; + -- end if; + -- end if; + --end process; + --q <= x; + + process (rst, clk, set, clr, en, aw, bw, cw, dw) + begin + if rising_edge(clk) then + if rst = '1' then + qw <= x"0000"; + elsif clr = '1' then + qw <= x"0000"; + elsif set = '1' then + qw <= x"beef"; + elsif en = '1' then + qw <= aw and bw and cw and dw; + end if; + end if; + end process; + +end behavioral; diff --git a/projects/experimental/srl.vhd b/projects/experimental/srl.vhd new file mode 100644 index 0000000..68eafe7 --- /dev/null +++ b/projects/experimental/srl.vhd @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + + +entity srl_experiments is + generic ( + A: std_logic_vector(3 downto 0) := "1010"; + B: std_logic_vector(3 downto 0) := "1100" + ); + port ( + clk_i: in std_logic; + clk_o: out std_logic + ); +end srl_experiments; + +architecture behavioral of srl_experiments is + + signal x_reg: std_logic := '0'; + signal clk_t: std_logic; + + signal idx: std_logic_vector(3 downto 0); + +begin + + process (clk_i, x_reg) + begin + if rising_edge(clk_i) then + if clk_t = '1' then + x_reg <= not x_reg; + end if; + end if; + end process; + + idx <= A when x_reg = '1' else B; + + e_srl: srlc16e + generic map (INIT => x"0001") + port map ( + clk => clk_i, + ce => '1', + + d => clk_t, + + a0 => idx(0), + a1 => idx(1), + a2 => idx(2), + a3 => idx(3), + + q => clk_t, + q15 => clk_o + ); + +end behavioral; + diff --git a/projects/experimental/tests/test_srl_experiment.vhd b/projects/experimental/tests/test_srl_experiment.vhd new file mode 100644 index 0000000..9858a46 --- /dev/null +++ b/projects/experimental/tests/test_srl_experiment.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; + + +entity test_srl_experiment is +end test_srl_experiment; + + +architecture behavior of test_srl_experiment is + + constant CLK_PERIOD: time := 20 ns; + + signal clk_i: std_logic; + signal clk_o: std_logic; + +begin + + e_uut: entity work.srl_experiments + generic map ( + A => "0100", + B => "0110" + ) + port map ( + clk_i => clk_i, + clk_o => clk_o + ); + + + p_clk: process + begin + clk_i <= '0'; + wait for CLK_PERIOD/2; + clk_i <= '1'; + wait for CLK_PERIOD/2; + end process; + +end; -- 2.43.0