From 8d0e816bbbe9c492c062588b506908781ff62b4d Mon Sep 17 00:00:00 2001 From: rs <> Date: Tue, 11 Nov 2025 23:18:27 -0600 Subject: [PATCH] Make naming convention more consistent --- libraries/nexys2/tests/nexys2_usb.vhd | 2 +- libraries/nexys2/usb.vhd | 66 +++++++++---------- .../{fifo_xclk.vhd => sync_fifo_2k_8.vhd} | 24 +++---- 3 files changed, 46 insertions(+), 46 deletions(-) rename libraries/utility/{fifo_xclk.vhd => sync_fifo_2k_8.vhd} (91%) diff --git a/libraries/nexys2/tests/nexys2_usb.vhd b/libraries/nexys2/tests/nexys2_usb.vhd index c8e4816..ec02f8c 100644 --- a/libraries/nexys2/tests/nexys2_usb.vhd +++ b/libraries/nexys2/tests/nexys2_usb.vhd @@ -56,7 +56,7 @@ begin rst_o => rst ); - e_usb: entity work.usb_cypress + e_usb: entity work.usb port map ( rst_i => rst, diff --git a/libraries/nexys2/usb.vhd b/libraries/nexys2/usb.vhd index 8a0956b..e6e0829 100644 --- a/libraries/nexys2/usb.vhd +++ b/libraries/nexys2/usb.vhd @@ -6,7 +6,7 @@ library utility; library work; -entity usb_cypress is +entity usb is generic (SYNC_STAGES: positive := 2); port ( rst_i: in std_logic; @@ -48,10 +48,10 @@ entity usb_cypress is stm_ul_ack_o: out std_logic; stm_ul_dat_i: in std_logic_vector(7 downto 0) ); -end usb_cypress; +end usb; -architecture behavioral of usb_cypress is +architecture behavioral of usb is signal ifclk_rst: std_logic; signal epp_rst: std_logic; @@ -68,14 +68,14 @@ architecture behavioral of usb_cypress is signal epp_wait: std_logic; -- Between USB mux and EPP interface, in epp_clk_i domain - signal xclk_eppen: std_logic; - signal xclk_astb: std_logic; - signal xclk_dstb: std_logic; - signal xclk_write: std_logic; - signal xclk_db_i: std_logic_vector(7 downto 0); - signal xclk_db_o: std_logic_vector(7 downto 0); - signal xclk_db_w: std_logic; - signal xclk_wait: std_logic; + signal sync_eppen: std_logic; + signal sync_astb: std_logic; + signal sync_dstb: std_logic; + signal sync_write: std_logic; + signal sync_db_i: std_logic_vector(7 downto 0); + signal sync_db_o: std_logic_vector(7 downto 0); + signal sync_db_w: std_logic; + signal sync_wait: std_logic; -- Between USB mux and STM interface signal dstm_ifclk: std_logic; @@ -176,58 +176,58 @@ begin -- EPP Interface -- EPP clock domain crossing - e_xclk_eppen: entity utility.sync_sig + e_sync_eppen: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES, INIT => '0') port map ( rst_i => epp_rst, clk_i => epp_clk_i, sig_i => epp_en, - sig_o => xclk_eppen + sig_o => sync_eppen ); - e_xclk_astb: entity utility.sync_sig + e_sync_astb: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => epp_clk_i, sig_i => epp_astb, - sig_o => xclk_astb + sig_o => sync_astb ); - e_xclk_dstb: entity utility.sync_sig + e_sync_dstb: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => epp_clk_i, sig_i => epp_dstb, - sig_o => xclk_dstb + sig_o => sync_dstb ); - e_xclk_wait: entity utility.sync_sig + e_sync_wait: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES, INIT => '0') -- FIXME: is this the best initial value for WAIT? port map ( rst_i => ifclk_rst, clk_i => DstmIFCLK, - sig_i => xclk_wait, + sig_i => sync_wait, sig_o => epp_wait ); -- These signals are stable during the time that they're validated by the -- synchronized handshaking signals, so no clock synchronizing is needed - xclk_write <= epp_write; - xclk_db_i <= epp_db_i; - epp_db_o <= xclk_db_o; - epp_db_w <= xclk_db_w; + sync_write <= epp_write; + sync_db_i <= epp_db_i; + epp_db_o <= sync_db_o; + epp_db_w <= sync_db_w; -- EPP interface logic e_epp: entity work.eppex_wb port map ( - EppEN => xclk_eppen, - EppAstb => xclk_astb, - EppDstb => xclk_dstb, - EppWr => xclk_write, - EppDB_i => xclk_db_i, - EppDB_o => xclk_db_o, - EppDB_w => xclk_db_w, - EppWait => xclk_wait, + EppEN => sync_eppen, + EppAstb => sync_astb, + EppDstb => sync_dstb, + EppWr => sync_write, + EppDB_i => sync_db_i, + EppDB_o => sync_db_o, + EppDB_w => sync_db_w, + EppWait => sync_wait, rst_i => epp_rst, clk_i => epp_clk_i, @@ -270,7 +270,7 @@ begin ); -- STM clock domain crossing, download side - e_dl_fifo: entity utility.fifo_xclk + e_dl_fifo: entity utility.sync_fifo_2k_8 generic map (SYNC_STAGES => SYNC_STAGES) port map ( head_rst_i => ifclk_rst, @@ -287,7 +287,7 @@ begin ); -- STM clock domain crossing, upload side - e_ul_fifo: entity utility.fifo_xclk + e_ul_fifo: entity utility.sync_fifo_2k_8 generic map (SYNC_STAGES => SYNC_STAGES) port map ( head_rst_i => stm_rst, diff --git a/libraries/utility/fifo_xclk.vhd b/libraries/utility/sync_fifo_2k_8.vhd similarity index 91% rename from libraries/utility/fifo_xclk.vhd rename to libraries/utility/sync_fifo_2k_8.vhd index 7ade367..f571922 100644 --- a/libraries/utility/fifo_xclk.vhd +++ b/libraries/utility/sync_fifo_2k_8.vhd @@ -1,5 +1,5 @@ -------------------------------------------------------------------------------- --- fifo_xclk - cross clock domain FIFO +-- sync_fifo_2k_8 - cross clock domain FIFO, 2048x8-bit -- -- Generics: -- SYNC_STAGES - number of shift register stages to use when synchronizing @@ -32,7 +32,7 @@ use unisim.vcomponents.all; library utility; -entity fifo_xclk is +entity sync_fifo_2k_8 is generic (SYNC_STAGES: positive := 2); port ( head_rst_i: in std_logic; @@ -47,13 +47,13 @@ entity fifo_xclk is tail_ack_i: in std_logic; tail_dat_o: out std_logic_vector(7 downto 0) ); -end fifo_xclk; +end sync_fifo_2k_8; -architecture behavioral of fifo_xclk is +architecture behavioral of sync_fifo_2k_8 is signal head_rst_wait: std_logic; - signal tail_adr_xclk: std_logic_vector(10 downto 0); + signal tail_adr_sync: std_logic_vector(10 downto 0); signal head_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); signal head_adr_next: std_logic_vector(10 downto 0); signal head_rdy: std_logic; @@ -61,7 +61,7 @@ architecture behavioral of fifo_xclk is signal is_full: std_logic; signal tail_rst_wait: std_logic; - signal head_adr_xclk: std_logic_vector(10 downto 0); + signal head_adr_sync: std_logic_vector(10 downto 0); signal tail_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); signal tail_adr_inc: std_logic_vector(10 downto 0); signal tail_adr_next: std_logic_vector(10 downto 0); @@ -81,15 +81,15 @@ begin sig_o => head_rst_wait ); - e_xclk_tail: entity utility.sync_vec + e_sync_tail: entity utility.sync_vec generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => head_clk_i, sig_i => std_logic_vector(tail_adr_reg), - sig_o => tail_adr_xclk + sig_o => tail_adr_sync ); - is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_xclk or + is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_sync or head_rst_i = '1' or head_rst_wait = '1' else '0'; @@ -119,15 +119,15 @@ begin sig_o => tail_rst_wait ); - e_xclk_head: entity utility.sync_vec + e_sync_head: entity utility.sync_vec generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => tail_clk_i, sig_i => std_logic_vector(head_adr_reg), - sig_o => head_adr_xclk + sig_o => head_adr_sync ); - is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_xclk or + is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_sync or tail_rst_i = '1' or tail_rst_wait = '1' else '0'; -- 2.43.0