From 6cefae32e1c8a5bdcc8ad379bf63ea0dc5c5075f Mon Sep 17 00:00:00 2001
From: rs <>
Date: Thu, 11 Dec 2025 02:45:56 -0600
Subject: [PATCH] Add enable output to pipe control logic

---
 libraries/dsp/pipectrl.vhd            | 3 +++
 libraries/dsp/pipectrl_runout.vhd     | 3 +++
 libraries/dsp/pipectrl_runout_srl.vhd | 3 +++
 libraries/dsp/pipectrl_split.vhd      | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index b07b22f..cde4634 100644
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -10,6 +10,8 @@ entity pipectrl is
 		rst_i: in  std_logic;
 		clk_i: in  std_logic;
 
+		en_o:  out std_logic;
+
 		stb_i: in  std_logic;
 		rdy_o: out std_logic;
 		dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -33,6 +35,7 @@ begin
 	-- * it is currently empty
 	-- * if the downstream stage is accepting the current data
 	enable <= (not stb_reg) or rdy_i;
+	en_o   <= enable and stb_i;
 
 	stb_o <= stb_reg;
 	rdy_o <= enable;
diff --git a/libraries/dsp/pipectrl_runout.vhd b/libraries/dsp/pipectrl_runout.vhd
index 097f847..2e9b7fd 100644
--- a/libraries/dsp/pipectrl_runout.vhd
+++ b/libraries/dsp/pipectrl_runout.vhd
@@ -10,6 +10,8 @@ entity pipectrl_runout is
 		rst_i: in  std_logic;
 		clk_i: in  std_logic;
 
+		en_o:  out std_logic;
+
 		stb_i: in  std_logic;
 		rdy_o: out std_logic;
 		dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -44,6 +46,7 @@ begin
 	dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
 	en      <= rdy_reg;
+	en_o    <= en and stb_i;
 	rob_en  <= rdy_reg and (not rdy_i);
 	rob_clr <= rdy_i;
 
diff --git a/libraries/dsp/pipectrl_runout_srl.vhd b/libraries/dsp/pipectrl_runout_srl.vhd
index 2213c7d..301d2f0 100644
--- a/libraries/dsp/pipectrl_runout_srl.vhd
+++ b/libraries/dsp/pipectrl_runout_srl.vhd
@@ -13,6 +13,8 @@ entity pipectrl_runout_srl is
 		rst_i: in  std_logic;
 		clk_i: in  std_logic;
 
+		en_o:  out std_logic;
+
 		stb_i: in  std_logic;
 		rdy_o: out std_logic;
 		dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -47,6 +49,7 @@ begin
 	--dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
 	en      <= rdy_reg;
+	en_o    <= en and stb_i;
 	rob_en  <= rdy_reg and (not rdy_i);
 	rob_clr <= rdy_i;
 
diff --git a/libraries/dsp/pipectrl_split.vhd b/libraries/dsp/pipectrl_split.vhd
index c3a0dd4..89fbd91 100644
--- a/libraries/dsp/pipectrl_split.vhd
+++ b/libraries/dsp/pipectrl_split.vhd
@@ -10,6 +10,8 @@ entity pipectrl_split is
 		rst_i:   in  std_logic;
 		clk_i:   in  std_logic;
 
+		en_o:    out std_logic;
+
 		stb_i:   in  std_logic;
 		rdy_o:   out std_logic;
 		dat_i:   in  std_logic_vector(WIDTH-1 downto 0);
@@ -43,6 +45,7 @@ begin
 	b_rdy <= (not b_stb_reg) or b_rdy_i;
 	load  <= a_rdy and b_rdy;
 	rdy_o <= load;
+	en_o  <= load and stb_i;
 
 	-- Full registers
 	process (rst_i, clk_i, load, a_rdy_i, b_rdy_i)
-- 
2.43.0