From 61d7e0d49e93ed0197068e07c74bb8f36ccd9ef4 Mon Sep 17 00:00:00 2001
From: Ryan <>
Date: Wed, 17 Sep 2025 16:23:28 -0500
Subject: [PATCH] Organize utility library

---
 libraries/utility/fifo.vhd              |   2 -
 libraries/utility/multiclk_ram.vhd      |  33 ----
 libraries/utility/tests/test_mapper.vhd | 202 ----------------------
 libraries/utility/wb_mapper.vhd         | 212 ------------------------
 libraries/utility/wb_mux2.vhd           |  43 -----
 libraries/utility/wb_mux4.vhd           |  97 -----------
 6 files changed, 589 deletions(-)
 delete mode 100644 libraries/utility/multiclk_ram.vhd
 delete mode 100644 libraries/utility/tests/test_mapper.vhd
 delete mode 100644 libraries/utility/wb_mapper.vhd
 delete mode 100644 libraries/utility/wb_mux2.vhd
 delete mode 100644 libraries/utility/wb_mux4.vhd

diff --git a/libraries/utility/fifo.vhd b/libraries/utility/fifo.vhd
index 303989f..b8feaa1 100644
--- a/libraries/utility/fifo.vhd
+++ b/libraries/utility/fifo.vhd
@@ -1,5 +1,3 @@
--- TODO: -- TODO: https://eecs.umich.edu/courses/doing_dsp/handout/SRL16E.pdf
---       Play with using shift-registers to make this more dense
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
diff --git a/libraries/utility/multiclk_ram.vhd b/libraries/utility/multiclk_ram.vhd
deleted file mode 100644
index 1a6cddb..0000000
--- a/libraries/utility/multiclk_ram.vhd
+++ /dev/null
@@ -1,33 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-entity multiclk_ram is
-	generic (
-		A: integer := 4;  -- Address width
-		N: integer := 8;  -- Data width
-	);
-	port (
-		-- The "native" clock domain, where the RAM itself lives
-		-- Read-only, and reads are asynchronous (clk_a_i is needed for signal domain crossing, not access)
-		clk_a_i: in  std_logic;
-		adr_a_i: in  std_logic_vector(A-1 downto 0);
-		dat_a_o: out std_logic_vector(N-1 downto 0);
-
-		-- The "external" clock domain, where the operator lives
-		-- Read and write
-		clk_b_i: in  std_logic;
-		stb_b_i: in  std_logic;
-		we_b_i:  in  std_logic;
-		ack_b_o: out std_logic;
-		adr_b_i: in  std_logic_vector(A-1 downto 0);
-		dat_b_i: in  std_logic_vector(N-1 downto 0);
-		dat_b_o: out std_logic_vector(N-1 downto 0);
-	);
-end multiclk_ram;
-
-
-architecture behavioral of multiclk_ram is
-begin
-end behavioral;
diff --git a/libraries/utility/tests/test_mapper.vhd b/libraries/utility/tests/test_mapper.vhd
deleted file mode 100644
index 5b033fc..0000000
--- a/libraries/utility/tests/test_mapper.vhd
+++ /dev/null
@@ -1,202 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-library work;
-
-
-entity test_mapper is
-end test_mapper;
-
-
-architecture behavior of test_mapper is
-
-	signal cyc:       std_logic;
-	signal stb:       std_logic;
-	signal we:        std_logic;
-	signal ack:       std_logic;
-	signal adr:       std_logic_vector(31 downto 0);
-	signal dat_mosi:  std_logic_vector(7 downto 0);
-	signal dat_miso:  std_logic_vector(7 downto 0);
-
-	signal mem_cyc:   std_logic;
-	signal mem_stb:   std_logic;
-	signal mem_we:    std_logic;
-	signal mem_ack:   std_logic;
-	signal mem_adr:   std_logic_vector(31 downto 0);
-	signal mem_mosi:  std_logic_vector(7 downto 0);
-	signal mem_miso:  std_logic_vector(7 downto 0);
-
-	signal tile_cyc:  std_logic;
-	signal tile_stb:  std_logic;
-	signal tile_we:   std_logic;
-	signal tile_ack:  std_logic;
-	signal tile_adr:  std_logic_vector(31 downto 0);
-	signal tile_mosi: std_logic_vector(7 downto 0);
-	signal tile_miso: std_logic_vector(7 downto 0);
-
-	signal host_cyc:  std_logic;
-	signal host_stb:  std_logic;
-	signal host_we:   std_logic;
-	signal host_ack:  std_logic;
-	signal host_adr:  std_logic_vector(31 downto 0);
-	signal host_mosi: std_logic_vector(7 downto 0);
-	signal host_miso: std_logic_vector(7 downto 0);
-
-	signal ps2_cyc:   std_logic;
-	signal ps2_stb:   std_logic;
-	signal ps2_we:    std_logic;
-	signal ps2_ack:   std_logic;
-	signal ps2_adr:   std_logic_vector(31 downto 0);
-	signal ps2_mosi:  std_logic_vector(7 downto 0);
-	signal ps2_miso:  std_logic_vector(7 downto 0);
-
-	signal uart_cyc:  std_logic;
-	signal uart_stb:  std_logic;
-	signal uart_we:   std_logic;
-	signal uart_ack:  std_logic;
-	signal uart_adr:  std_logic_vector(31 downto 0);
-	signal uart_mosi: std_logic_vector(7 downto 0);
-	signal uart_miso: std_logic_vector(7 downto 0);
-
-begin
-
-	p_test: process
-	begin
-		-- Initial values
-		cyc       <= '0';
-		stb       <= '0';
-		we        <= '0';
-		adr       <= x"00000000";
-		dat_mosi  <= x"00";
-		mem_miso  <= x"11";
-		tile_miso <= x"aa";
-		host_miso <= x"bb";
-		ps2_miso  <= x"cc";
-		uart_miso <= x"dd";
-		mem_ack   <= '0';
-		tile_ack  <= '0';
-		host_ack  <= '0';
-		ps2_ack   <= '0';
-		uart_ack  <= '0';
-
-		cyc      <= '1';
-		stb      <= '1';
-		we       <= '0';
-		adr      <= x"00000000";
-		dat_mosi <= x"00";
-
-		wait for 100 ns;
-
-		cyc      <= '1';
-		stb      <= '1';
-		we       <= '0';
-		adr      <= x"02000000";
-		dat_mosi <= x"00";
-
-		-- Done
-		wait;
-	end process;
-
-	e_uut: entity work.wb_mapper
-		generic map (
-			A_WIDTH => 32,
-			D_WIDTH => 8
-		)
-		port map (
-			cyc_i   => cyc,
-			stb_i   => stb,
-			we_i    => we,
-			ack_o   => ack,
-			adr_i   => adr,
-			dat_i   => dat_mosi,
-			dat_o   => dat_miso,
-
-			-- Flash: 0x00000000-0x00ffffff
-			-- Ram:   0x01000000-0x01ffffff
-			mask_0  => "00000010000000000000000000000000",
-			match_0 => "00000000000000000000000000000000",
-			cyc_o_0 => mem_cyc,
-			stb_o_0 => mem_stb,
-			we_o_0  => mem_we,
-			ack_i_0 => mem_ack,
-			adr_o_0 => mem_adr,
-			dat_o_0 => mem_mosi,
-			dat_i_0 => mem_miso,
-
-			-- Vbuf:  0x02000000-0x02001fff
-			-- Tiles: 0x02002000-0x02003fff
-			mask_1  => "00000010000000000100000000000000",
-			match_1 => "00000010000000000000000000000000",
-			cyc_o_1 => tile_cyc,
-			stb_o_1 => tile_stb,
-			we_o_1  => tile_we,
-			ack_i_1 => tile_ack,
-			adr_o_1 => tile_adr,
-			dat_o_1 => tile_mosi,
-			dat_i_1 => tile_miso,
-
-			-- Host:  0x02004000-0x02004007
-			mask_2  => "00000010000000000100000000011000",
-			match_2 => "00000010000000000100000000000000",
-			cyc_o_2 => host_cyc,
-			stb_o_2 => host_stb,
-			we_o_2  => host_we,
-			ack_i_2 => host_ack,
-			adr_o_2 => host_adr,
-			dat_o_2 => host_mosi,
-			dat_i_2 => host_miso,
-
-			-- PS2:   0x02004008-0x0200400f
-			mask_3  => "00000010000000000100000000011000",
-			match_3 => "00000010000000000100000000001000",
-			cyc_o_3 => ps2_cyc,
-			stb_o_3 => ps2_stb,
-			we_o_3  => ps2_we,
-			ack_i_3 => ps2_ack,
-			adr_o_3 => ps2_adr,
-			dat_o_3 => ps2_mosi,
-			dat_i_3 => ps2_miso,
-
-			-- UART:  0x02004010-0x02004017
-			mask_4  => "00000010000000000100000000011000",
-			match_4 => "00000010000000000100000000010000",
-			cyc_o_4 => uart_cyc,
-			stb_o_4 => uart_stb,
-			we_o_4  => uart_we,
-			ack_i_4 => uart_ack,
-			adr_o_4 => uart_adr,
-			dat_o_4 => uart_mosi,
-			dat_i_4 => uart_miso,
-
-			mask_5  => "00000000000000000000000000000000",
-			match_5 => "00000000000000000000000000000001",
-			cyc_o_5 => open,
-			stb_o_5 => open,
-			we_o_5  => open,
-			ack_i_5 => '1',
-			adr_o_5 => open,
-			dat_o_5 => open,
-			dat_i_5 => "00000000",
-
-			mask_6  => "00000000000000000000000000000000",
-			match_6 => "00000000000000000000000000000001",
-			cyc_o_6 => open,
-			stb_o_6 => open,
-			we_o_6  => open,
-			ack_i_6 => '1',
-			adr_o_6 => open,
-			dat_o_6 => open,
-			dat_i_6 => "00000000",
-
-			mask_7  => "00000000000000000000000000000000",
-			match_7 => "00000000000000000000000000000001",
-			cyc_o_7 => open,
-			stb_o_7 => open,
-			we_o_7  => open,
-			ack_i_7 => '1',
-			adr_o_7 => open,
-			dat_o_7 => open,
-			dat_i_7 => "00000000"
-		);
-
-end;
diff --git a/libraries/utility/wb_mapper.vhd b/libraries/utility/wb_mapper.vhd
deleted file mode 100644
index 87f68ff..0000000
--- a/libraries/utility/wb_mapper.vhd
+++ /dev/null
@@ -1,212 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity wb_mapper is
-	generic (
-		A_WIDTH: integer := 32;
-		D_WIDTH: integer := 8
-	);
-	port (
-		-- Master Wishbone interface
-		cyc_i:   in  std_logic;
-		stb_i:   in  std_logic;
-		we_i:    in  std_logic;
-		ack_o:   out std_logic;
-		adr_i:   in  std_logic_vector(31 downto 0);
-		dat_i:   in  std_logic_vector(7 downto 0);
-		dat_o:   out std_logic_vector(7 downto 0);
-
-		-- Device wishbone interfaces
-		mask_0:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_0: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_0: out std_logic;
-		stb_o_0: out std_logic;
-		we_o_0:  out std_logic;
-		ack_i_0: in  std_logic;
-		adr_o_0: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_0: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_0: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_1:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_1: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_1: out std_logic;
-		stb_o_1: out std_logic;
-		we_o_1:  out std_logic;
-		ack_i_1: in  std_logic;
-		adr_o_1: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_1: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_1: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_2:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_2: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_2: out std_logic;
-		stb_o_2: out std_logic;
-		we_o_2:  out std_logic;
-		ack_i_2: in  std_logic;
-		adr_o_2: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_2: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_2: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_3:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_3: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_3: out std_logic;
-		stb_o_3: out std_logic;
-		we_o_3:  out std_logic;
-		ack_i_3: in  std_logic;
-		adr_o_3: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_3: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_3: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_4:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_4: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_4: out std_logic;
-		stb_o_4: out std_logic;
-		we_o_4:  out std_logic;
-		ack_i_4: in  std_logic;
-		adr_o_4: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_4: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_4: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_5:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_5: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_5: out std_logic;
-		stb_o_5: out std_logic;
-		we_o_5:  out std_logic;
-		ack_i_5: in  std_logic;
-		adr_o_5: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_5: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_5: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_6:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_6: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_6: out std_logic;
-		stb_o_6: out std_logic;
-		we_o_6:  out std_logic;
-		ack_i_6: in  std_logic;
-		adr_o_6: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_6: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_6: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		mask_7:  in  std_logic_vector(A_WIDTH-1 downto 0);
-		match_7: in  std_logic_vector(A_WIDTH-1 downto 0);
-		cyc_o_7: out std_logic;
-		stb_o_7: out std_logic;
-		we_o_7:  out std_logic;
-		ack_i_7: in  std_logic;
-		adr_o_7: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_7: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_7: in  std_logic_vector(D_WIDTH-1 downto 0)
-	);
-end wb_mapper;
-
-
-architecture behavioral of wb_mapper is
-
-	signal sel_0: std_logic;
-	signal sel_1: std_logic;
-	signal sel_2: std_logic;
-	signal sel_3: std_logic;
-	signal sel_4: std_logic;
-	signal sel_5: std_logic;
-	signal sel_6: std_logic;
-	signal sel_7: std_logic;
-	signal dummy: std_logic;
-
-	signal en_0:  std_logic_vector(7 downto 0);
-	signal en_1:  std_logic_vector(7 downto 0);
-	signal en_2:  std_logic_vector(7 downto 0);
-	signal en_3:  std_logic_vector(7 downto 0);
-	signal en_4:  std_logic_vector(7 downto 0);
-	signal en_5:  std_logic_vector(7 downto 0);
-	signal en_6:  std_logic_vector(7 downto 0);
-	signal en_7:  std_logic_vector(7 downto 0);
-
-begin
-
-	sel_0   <= '1' when (adr_i and mask_0) = match_0 else '0';
-	en_0    <= (others => sel_0);
-	cyc_o_0 <= cyc_i and sel_0;
-	stb_o_0 <= stb_i;
-	we_o_0  <= we_i;
-	adr_o_0 <= adr_i;
-	dat_o_0 <= dat_i;
-
-	sel_1   <= '1' when (adr_i and mask_1) = match_1 else '0';
-	en_1    <= (others => sel_1);
-	cyc_o_1 <= cyc_i and sel_1;
-	stb_o_1 <= stb_i;
-	we_o_1  <= we_i;
-	adr_o_1 <= adr_i;
-	dat_o_1 <= dat_i;
-
-	sel_2   <= '1' when (adr_i and mask_2) = match_2 else '0';
-	en_2    <= (others => sel_2);
-	cyc_o_2 <= cyc_i and sel_2;
-	stb_o_2 <= stb_i;
-	we_o_2  <= we_i;
-	adr_o_2 <= adr_i;
-	dat_o_2 <= dat_i;
-
-	sel_3   <= '1' when (adr_i and mask_3) = match_3 else '0';
-	en_3    <= (others => sel_3);
-	cyc_o_3 <= cyc_i and sel_3;
-	stb_o_3 <= stb_i;
-	we_o_3  <= we_i;
-	adr_o_3 <= adr_i;
-	dat_o_3 <= dat_i;
-
-	sel_4   <= '1' when (adr_i and mask_4) = match_4 else '0';
-	en_4    <= (others => sel_4);
-	cyc_o_4 <= cyc_i and sel_4;
-	stb_o_4 <= stb_i;
-	we_o_4  <= we_i;
-	adr_o_4 <= adr_i;
-	dat_o_4 <= dat_i;
-
-	sel_5   <= '1' when (adr_i and mask_5) = match_5 else '0';
-	en_5    <= (others => sel_5);
-	cyc_o_5 <= cyc_i and sel_5;
-	stb_o_5 <= stb_i;
-	we_o_5  <= we_i;
-	adr_o_5 <= adr_i;
-	dat_o_5 <= dat_i;
-
-	sel_6   <= '1' when (adr_i and mask_6) = match_6 else '0';
-	en_6    <= (others => sel_6);
-	cyc_o_6 <= cyc_i and sel_6;
-	stb_o_6 <= stb_i;
-	we_o_6  <= we_i;
-	adr_o_6 <= adr_i;
-	dat_o_6 <= dat_i;
-
-	sel_7   <= '1' when (adr_i and mask_7) = match_7 else '0';
-	en_7    <= (others => sel_7);
-	cyc_o_7 <= cyc_i and sel_7;
-	stb_o_7 <= stb_i;
-	we_o_7  <= we_i;
-	adr_o_7 <= adr_i;
-	dat_o_7 <= dat_i;
-
-	dummy <= not (sel_0 or sel_1 or sel_2 or sel_3 or sel_4 or sel_5 or sel_6 or sel_7);
-
-	ack_o <= (ack_i_0 and sel_0) or
-	         (ack_i_1 and sel_1) or
-	         (ack_i_2 and sel_2) or
-	         (ack_i_3 and sel_3) or
-	         (ack_i_4 and sel_4) or
-	         (ack_i_5 and sel_5) or
-	         (ack_i_6 and sel_6) or
-	         (ack_i_7 and sel_7) or
-	         dummy;  -- If none are selected, acknowledge to eat the bus transaction
-
-	dat_o <= (dat_i_0 and en_0) or
-	         (dat_i_1 and en_1) or
-	         (dat_i_2 and en_2) or
-	         (dat_i_3 and en_3) or
-	         (dat_i_4 and en_4) or
-	         (dat_i_5 and en_5) or
-	         (dat_i_6 and en_6) or
-	         (dat_i_7 and en_7);
-
-end behavioral;
diff --git a/libraries/utility/wb_mux2.vhd b/libraries/utility/wb_mux2.vhd
deleted file mode 100644
index e0eb31d..0000000
--- a/libraries/utility/wb_mux2.vhd
+++ /dev/null
@@ -1,43 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity wb_mux2 is
-	generic (
-		WIDTH: integer := 8
-	);
-	port (
-		sel:     in  std_logic;
-
-		-- Single master
-		cyc_i:   in  std_logic;
-		ack_o:   out std_logic;
-		dat_o:   out std_logic_vector(WIDTH-1 downto 0);
-
-		-- Multiple devices
-		cyc_o_0: out std_logic;
-		ack_i_0: in  std_logic;
-		dat_i_0: in  std_logic_vector(WIDTH-1 downto 0);
-
-		cyc_o_1: out std_logic;
-		ack_i_1: in  std_logic;
-		dat_i_1: in  std_logic_vector(WIDTH-1 downto 0)
-	);
-end wb_mux2;
-
-
-architecture behavioral of wb_mux2 is
-begin
-
-	cyc_o_0 <= cyc_i when sel  = '0' else '0';
-	cyc_o_1 <= cyc_i when sel /= '0' else '0';
-
-	with sel select dat_o <=
-		dat_i_0 when '0',
-		dat_i_1 when others;
-
-	with sel select ack_o <=
-		ack_i_0 when '0',
-		ack_i_1 when others;
-
-end behavioral;
diff --git a/libraries/utility/wb_mux4.vhd b/libraries/utility/wb_mux4.vhd
deleted file mode 100644
index 53bf871..0000000
--- a/libraries/utility/wb_mux4.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity wb_mux4 is
-	generic (
-		A_WIDTH: integer := 32;
-		D_WIDTH: integer := 8
-	);
-	port (
-		sel:   in  std_logic_vector(1 downto 0);
-
-		-- Wishbone interface to master
-		cyc_i: in  std_logic;
-		stb_i: in  std_logic;
-		we_i:  in  std_logic;
-		ack_o: out std_logic;
-		adr_i: in  std_logic_vector(A_WIDTH-1 downto 0);
-		dat_i: in  std_logic_vector(D_WIDTH-1 downto 0);
-		dat_o: out std_logic_vector(D_WIDTH-1 downto 0);
-
-		-- Wishbone interfaces to devices
-		cyc_o_0: out std_logic;
-		stb_o_0: out std_logic;
-		we_o_0:  in  std_logic;
-		ack_i_0: out std_logic;
-		adr_o_0: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_0: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_0: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		cyc_o_1: out std_logic;
-		stb_o_1: out std_logic;
-		we_o_1:  in  std_logic;
-		ack_i_1: out std_logic;
-		adr_o_1: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_1: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_1: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		cyc_o_2: out std_logic;
-		stb_o_2: out std_logic;
-		we_o_2:  in  std_logic;
-		ack_i_2: out std_logic;
-		adr_o_2: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_2: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_2: in  std_logic_vector(D_WIDTH-1 downto 0);
-
-		cyc_o_3: out std_logic;
-		stb_o_3: out std_logic;
-		we_o_3:  in  std_logic;
-		ack_i_3: out std_logic;
-		adr_o_3: out std_logic_vector(A_WIDTH-1 downto 0);
-		dat_o_3: out std_logic_vector(D_WIDTH-1 downto 0);
-		dat_i_3: in  std_logic_vector(D_WIDTH-1 downto 0)
-	);
-end wb_mux4;
-
-
-architecture behavioral of wb_mux4 is
-begin
-
-	cyc_o_0 <= cyc_i when sel = "00" else '0';
-	stb_o_0 <= stb_i;
-	we_o_0  <= we_i;
-	adr_o_0 <= adr_i;
-	dat_o_0 <= dat_i;
-
-	cyc_o_1 <= cyc_i when sel = "01" else '0';
-	stb_o_1 <= stb_i;
-	we_o_1  <= we_i;
-	adr_o_1 <= adr_i;
-	dat_o_1 <= dat_i;
-
-	cyc_o_2 <= cyc_i when sel = "10" else '0';
-	stb_o_2 <= stb_i;
-	we_o_2  <= we_i;
-	adr_o_2 <= adr_i;
-	dat_o_2 <= dat_i;
-
-	cyc_o_3 <= cyc_i when sel = "11" else '0';
-	stb_o_3 <= stb_i;
-	we_o_3  <= we_i;
-	adr_o_3 <= adr_i;
-	dat_o_3 <= dat_i;
-
-	with sel select ack_o <=
-		ack_i_0 when "00",
-		ack_i_1 when "01",
-		ack_i_2 when "10",
-		ack_i_3 when others;
-
-	with sel select dat_o <=
-		dat_i_0 when "00",
-		dat_i_1 when "01",
-		dat_i_2 when "10",
-		dat_i_3 when others;
-
-end behavioral;
-- 
2.43.0