From 5f794a0be189b828e11c5eda916370839954c78f Mon Sep 17 00:00:00 2001
From: rs <>
Date: Thu, 11 Dec 2025 21:08:51 -0600
Subject: [PATCH] Fix type issues and typo in sum block

---
 libraries/dsp/pcm16_2ch_sum.vhd | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/libraries/dsp/pcm16_2ch_sum.vhd b/libraries/dsp/pcm16_2ch_sum.vhd
index 9213801..369f26a 100644
--- a/libraries/dsp/pcm16_2ch_sum.vhd
+++ b/libraries/dsp/pcm16_2ch_sum.vhd
@@ -11,7 +11,7 @@ entity pcm16_2ch_sum is
 		clk_i:   in  std_logic;
 
 		a_stb_i: in  std_logic;
-		a_rdy_i: out std_logic;
+		a_rdy_o: out std_logic;
 		a_dat_i: in  std_logic_vector(31 downto 0);
 
 		b_stb_i: in  std_logic;
@@ -48,21 +48,21 @@ architecture behavioral of pcm16_2ch_sum is
 
 begin
 
-	samp_a_l <= a_dat_i(15 downto  0);
-	samp_a_r <= a_dat_i(31 downto 16);
-	samp_b_l <= b_dat_i(15 downto  0);
-	samp_b_r <= b_dat_i(31 downto 16);
+	samp_a_l <= signed(a_dat_i(15 downto  0));
+	samp_a_r <= signed(a_dat_i(31 downto 16));
+	samp_b_l <= signed(b_dat_i(15 downto  0));
+	samp_b_r <= signed(b_dat_i(31 downto 16));
 
 	result_l <= samp_a_l + samp_b_l;
 	result_r <= samp_a_r + samp_b_r;
 
 	e_sat_l: entity work.saturate
 		generic map (WIDTH_IN => 17, WIDTH_OUT => 16)
-		port map (dat_i => result_l, dat_o => sat_l);
+		port map (dat_i => std_logic_vector(result_l), dat_o => sat_l);
 
 	e_sat_r: entity work.saturate
 		generic map (WIDTH_IN => 17, WIDTH_OUT => 16)
-		port map (dat_i => result_r, dat_o => sat_r);
+		port map (dat_i => std_logic_vector(result_r), dat_o => sat_r);
 
 	result <= sat_r & sat_l;
 
-- 
2.43.0