From 22513a9982ada79c3e489794b9c6d432f4da39c2 Mon Sep 17 00:00:00 2001
From: rs <>
Date: Sat, 28 Jun 2025 00:18:50 -0500
Subject: [PATCH] Add documentation to VGA interface

---
 libraries/vga/vga_counter.vhd |  4 ++++
 libraries/vga/vga_tiler.vhd   | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/libraries/vga/vga_counter.vhd b/libraries/vga/vga_counter.vhd
index 907188e..8f3d400 100644
--- a/libraries/vga/vga_counter.vhd
+++ b/libraries/vga/vga_counter.vhd
@@ -1,3 +1,7 @@
+--------------------------------------------------------------------------------
+-- vga_counter - pixel counter and sync generator for VGA interfaces
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/libraries/vga/vga_tiler.vhd b/libraries/vga/vga_tiler.vhd
index ae45160..52225c0 100644
--- a/libraries/vga/vga_tiler.vhd
+++ b/libraries/vga/vga_tiler.vhd
@@ -1,3 +1,36 @@
+--------------------------------------------------------------------------------
+-- vga_tiler - tile-based graphics controller for VGA interfaces
+--------------------------------------------------------------------------------
+-- 0x0000 - 0x2000: Screen buffer
+--                  Each byte is an index into tile memory
+--                  Byte 0 is the top-left tile
+-- 0x2000 - 0x27ff: Tile data
+--                  Each tile is 8x8 pixels and consists of 8 bytes
+--                  The first byte of a tile is the top row, one pixel per bit
+--                  At startup, a subset of the Commodore64 font is loaded into
+--                  tile memory, mapped to appropriate ASCII characters
+--------------------------------------------------------------------------------
+-- WISHBONE DATASHEET
+--
+-- Wishbone specification used: Rev B.3
+-- Interface type: device
+-- Port size: 8-bit
+-- Operand sizes: 8-bit
+-- Endianness: undefined (port size same as granularity)
+-- Data transfer sequence: undefined
+-- Clock constraints: 50 MHz expected
+-- Signals:
+-- * rst_i
+-- * clk_i
+-- * cyc_i
+-- * stb_i
+-- * we_i
+-- * ack_o
+-- * adr_i (14-bit)
+-- * dat_i (8-bit)
+-- * dat_o (8-bit)
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_misc.all;
-- 
2.43.0