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rs [Thu, 28 Aug 2025 18:37:19 +0000 (13:37 -0500)]
Add RO simulated flash and simulation utilities
rs [Sat, 23 Aug 2025 16:46:07 +0000 (11:46 -0500)]
Remove debug print
rs [Thu, 3 Jul 2025 04:59:16 +0000 (23:59 -0500)]
Add scripts to single-step cpu from host
rs [Thu, 3 Jul 2025 04:58:44 +0000 (23:58 -0500)]
Update test programs
rs [Thu, 3 Jul 2025 04:57:27 +0000 (23:57 -0500)]
Update project
* Add single stepping back to CPU
* Separate flash and RAM cyc signals
* Add timers
* Fix interrupt bug
rs [Thu, 3 Jul 2025 04:55:18 +0000 (23:55 -0500)]
Add align assembler directive
rs [Sun, 29 Jun 2025 22:20:26 +0000 (17:20 -0500)]
Separate CYC for flash and ram in mem controller
rs [Sun, 29 Jun 2025 10:24:19 +0000 (05:24 -0500)]
Move power-on-reset into host_ctrl
rs [Sun, 29 Jun 2025 09:39:36 +0000 (04:39 -0500)]
Add new Wishbone address mapper
rs [Sun, 29 Jun 2025 09:37:41 +0000 (04:37 -0500)]
Update cpu0 test programs
rs [Sun, 29 Jun 2025 09:35:53 +0000 (04:35 -0500)]
Remove trailing whitespace
rs [Sat, 28 Jun 2025 05:42:31 +0000 (00:42 -0500)]
Add Wishbone docs to cpu and remove debug signals
rs [Sat, 28 Jun 2025 05:18:50 +0000 (00:18 -0500)]
Add documentation to VGA interface
rs [Sat, 28 Jun 2025 05:18:29 +0000 (00:18 -0500)]
Add Wishbone datasheet to RS232 UART
rs [Sat, 28 Jun 2025 05:01:44 +0000 (00:01 -0500)]
Add more documentation for PS2 and RS232 ifaces
rs [Sat, 28 Jun 2025 04:53:56 +0000 (23:53 -0500)]
Add documentation in nexys2 library
rs [Sat, 28 Jun 2025 03:25:41 +0000 (22:25 -0500)]
Add license
rs [Sat, 28 Jun 2025 03:19:34 +0000 (22:19 -0500)]
Initial commit
projects / vhdl / log