From: rs <>
Date: Fri, 12 Dec 2025 03:06:51 +0000 (-0600)
Subject: Rename ACK to RDY in merge pipeline control block
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=dd1a74ab322b2feb6c571e68c4c643a94f73298e;p=vhdl

Rename ACK to RDY in merge pipeline control block
---

diff --git a/libraries/dsp/merge.vhd b/libraries/dsp/merge.vhd
index 9fc6dd0..db51450 100644
--- a/libraries/dsp/merge.vhd
+++ b/libraries/dsp/merge.vhd
@@ -19,13 +19,13 @@ use unisim.vcomponents.all;
 entity merge is
 	port (
 		a_stb_i: in  std_logic;
-		a_ack_o: out std_logic;
+		a_rdy_o: out std_logic;
 
 		b_stb_i: in  std_logic;
-		b_ack_o: out std_logic;
+		b_rdy_o: out std_logic;
 
 		stb_o:   out std_logic;
-		ack_i:   in  std_logic
+		rdy_i:   in  std_logic
 	);
 end merge;
 
@@ -38,7 +38,7 @@ begin
 
 	costrobe <= a_stb_i and b_stb_i;
 	stb_o    <= costrobe;
-	a_ack_o  <= costrobe and ack_i;
-	b_ack_o  <= costrobe and ack_i;
+	a_rdy_o  <= costrobe and rdy_i;
+	b_rdy_o  <= costrobe and rdy_i;
 
 end behavioral;