From: rs <>
Date: Sun, 29 Jun 2025 09:39:36 +0000 (-0500)
Subject: Add new Wishbone address mapper
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=c5b61c48be4cf5507de2a256b1db26501cb9bec8;p=vhdl

Add new Wishbone address mapper
---

diff --git a/libraries/utility/tests/test_wb_mapper_a32d8.vhd b/libraries/utility/tests/test_wb_mapper_a32d8.vhd
new file mode 100644
index 0000000..1c70b6d
--- /dev/null
+++ b/libraries/utility/tests/test_wb_mapper_a32d8.vhd
@@ -0,0 +1,716 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+
+
+entity test_wb_mapper_a32d8 is
+end test_wb_mapper_a32d8;
+
+
+architecture behavior of test_wb_mapper_a32d8 is
+
+	signal cyc:      std_logic;
+	signal ack:      std_logic;
+	signal adr:      std_logic_vector(31 downto 0);
+	signal dat:      std_logic_vector(7 downto 0);
+
+	signal cyc_mem:  std_logic;
+	signal ack_mem:  std_logic;
+	signal dat_mem:  std_logic_vector(7 downto 0);
+
+	signal cyc_tile: std_logic;
+	signal ack_tile: std_logic;
+	signal dat_tile: std_logic_vector(7 downto 0);
+
+	signal cyc_host: std_logic;
+	signal ack_host: std_logic;
+	signal dat_host: std_logic_vector(7 downto 0);
+
+	signal cyc_ps2:  std_logic;
+	signal ack_ps2:  std_logic;
+	signal dat_ps2:  std_logic_vector(7 downto 0);
+
+	signal cyc_uart: std_logic;
+	signal ack_uart: std_logic;
+	signal dat_uart: std_logic_vector(7 downto 0);
+
+begin
+
+	p_test: process
+	begin
+		-- Initial values
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+
+		dat_mem  <= x"01";
+		dat_tile <= x"02";
+		dat_host <= x"04";
+		dat_ps2  <= x"08";
+		dat_uart <= x"10";
+
+		------------------------------------------------------------------------
+		-- Test memory map range
+		-- 0x00000000 - 0x01ffffff
+		adr <= x"00000000";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1'   report "ack";
+		assert cyc_mem  = '1'   report "cyc";
+		assert cyc_tile = '0'   report "wrong cyc";
+		assert cyc_host = '0'   report "wrong cyc";
+		assert cyc_ps2  = '0'   report "wrong cyc";
+		assert cyc_uart = '0'   report "wrong cyc";
+		assert dat      = x"01" report "dat";
+
+		-- Block acks from other devices
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"00001000";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '1';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"01";
+
+		-- Block acks from other devices
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"01ffffff";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '1';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"01";
+
+		-- Block acks from other devices
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		------------------------------------------------------------------------
+		-- Test tiler map range
+		-- 0x02000000 - 0x02003fff
+		adr <= x"02000000";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1' report "a";
+		assert cyc_mem  = '0' report "b";
+		assert cyc_tile = '1' report "c";
+		assert cyc_host = '0' report "d";
+		assert cyc_ps2  = '0' report "e";
+		assert cyc_uart = '0' report "f";
+		assert dat      = x"02" report "g";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02001000";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '1';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"02";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02003fff";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '1';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"02";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		------------------------------------------------------------------------
+		-- Test host map range
+		-- 0x02004000 - 0x02004007
+		adr <= x"02004000";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '1';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"04";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02004003";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '1';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"04";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02004007";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '1';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+		assert dat      = x"04";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		------------------------------------------------------------------------
+		-- Test ps2 map range
+		-- 0x02004008 - 0x0200400f
+		adr <= x"02004008";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '1';
+		assert cyc_uart = '0';
+		assert dat      = x"08";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"0200400b";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '1';
+		assert cyc_uart = '0';
+		assert dat      = x"08";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"0200400f";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '1';
+		assert cyc_uart = '0';
+		assert dat      = x"08";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		------------------------------------------------------------------------
+		-- Test uart map range
+		-- 0x02004010 - 0x02004017
+		adr <= x"02004010";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '1';
+		assert dat      = x"10";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02004013";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '1';
+		assert dat      = x"10";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		adr <= x"02004017";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle out only sent to proper device
+		-- Ack comes from proper device
+		-- Dat comes from proper device
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '1';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '1';
+		assert dat      = x"10";
+
+		-- Block acks from other devices
+		ack_mem  <= '1';
+		ack_tile <= '1';
+		ack_host <= '1';
+		ack_ps2  <= '1';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '0';
+
+		------------------------------------------------------------------------
+		-- Test out-of-bounds
+		adr <= x"02004018";
+
+		-- No cycle out when no cycle in
+		cyc <= '0';
+		wait for 1 ns;
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		-- Cycle not sent to any device
+		-- Ack always asserted to eat transaction
+		cyc <= '1';
+		ack_mem  <= '0';
+		ack_tile <= '0';
+		ack_host <= '0';
+		ack_ps2  <= '0';
+		ack_uart <= '0';
+		wait for 1 ns;
+		assert ack      = '1';
+		assert cyc_mem  = '0';
+		assert cyc_tile = '0';
+		assert cyc_host = '0';
+		assert cyc_ps2  = '0';
+		assert cyc_uart = '0';
+
+		------------------------------------------------------------------------
+		-- Done
+		wait;
+	end process;
+
+
+	e_uut: entity work.wb_mapper_a32d8
+		generic map (
+			N => 5
+		)
+		port map (
+			cyc_i    => cyc,
+			ack_o    => ack,
+			adr_i    => adr,
+			dat_o    => dat,
+
+			mask(0)  => "00000010000000000000000000000000",
+			mask(1)  => "00000010000000000100000000000000",
+			mask(2)  => "00000010000000000100000000011000",
+			mask(3)  => "00000010000000000100000000011000",
+			mask(4)  => "00000010000000000100000000011000",
+
+			match(0) => "00000000000000000000000000000000",
+			match(1) => "00000010000000000000000000000000",
+			match(2) => "00000010000000000100000000000000",
+			match(3) => "00000010000000000100000000001000",
+			match(4) => "00000010000000000100000000010000",
+
+			cyc_o(0) => cyc_mem,
+			cyc_o(1) => cyc_tile,
+			cyc_o(2) => cyc_host,
+			cyc_o(3) => cyc_ps2,
+			cyc_o(4) => cyc_uart,
+
+			ack_i(0) => ack_mem,
+			ack_i(1) => ack_tile,
+			ack_i(2) => ack_host,
+			ack_i(3) => ack_ps2,
+			ack_i(4) => ack_uart,
+
+			dat_i(0) => dat_mem,
+			dat_i(1) => dat_tile,
+			dat_i(2) => dat_host,
+			dat_i(3) => dat_ps2,
+			dat_i(4) => dat_uart
+		);
+
+end;
diff --git a/libraries/utility/types.vhd b/libraries/utility/types.vhd
new file mode 100644
index 0000000..435c75c
--- /dev/null
+++ b/libraries/utility/types.vhd
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+package types is
+
+	subtype slv8 is std_logic_vector(7 downto 0);
+	type slv8_array is array(natural range <>) of slv8;
+
+	subtype slv16 is std_logic_vector(15 downto 0);
+	type slv16_array is array(natural range <>) of slv16;
+
+	subtype slv32 is std_logic_vector(31 downto 0);
+	type slv32_array is array(natural range <>) of slv32;
+
+	subtype slv64 is std_logic_vector(63 downto 0);
+	type slv64_array is array(natural range <>) of slv64;
+
+end types;
+
+
+package body types is
+end types;
diff --git a/libraries/utility/wb_mapper_a32d8.vhd b/libraries/utility/wb_mapper_a32d8.vhd
new file mode 100644
index 0000000..7767826
--- /dev/null
+++ b/libraries/utility/wb_mapper_a32d8.vhd
@@ -0,0 +1,59 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+
+library work;
+use work.types.all;
+
+
+entity wb_mapper_a32d8 is
+	generic (
+		N: integer := 8
+	);
+	port (
+		-- Master interface
+		cyc_i: in  std_logic;
+		ack_o: out std_logic;
+		adr_i: in  slv32;
+		dat_o: out slv8;
+
+		-- Configuration
+		mask:  in  slv32_array(N-1 downto 0);
+		match: in  slv32_array(N-1 downto 0);
+
+		-- Device interfaces
+		cyc_o: out std_logic_vector(N-1 downto 0);
+		ack_i: in  std_logic_vector(N-1 downto 0);
+		dat_i: in  slv8_array(N-1 downto 0)
+	);
+end wb_mapper_a32d8;
+
+
+architecture behavioral of wb_mapper_a32d8 is
+
+	signal sel:   std_logic_vector(N-1 downto 0);
+	signal dummy: std_logic;
+
+begin
+
+	g_sel: for n in 0 to n-1 generate
+		sel(n) <= '1' when (adr_i and mask(n)) = match(n) else '0';
+	end generate;
+	dummy <= not or_reduce(sel);
+
+	cyc_o <= sel when cyc_i = '1' else (others => '0');
+	ack_o <= or_reduce(sel and ack_i) or dummy;
+
+	process (sel, dat_i)
+		variable temp: slv8 := (others => '0');
+	begin
+		temp := (others => '0');
+		for n in 0 to N-1 loop
+			if sel(n) = '1' then
+				temp := temp or dat_i(n);
+			end if;
+		end loop;
+		dat_o <= temp;
+	end process;
+
+end behavioral;
diff --git a/projects/cpu_0/nexys2.vhd b/projects/cpu_0/nexys2.vhd
index 24662fe..53ced7e 100644
--- a/projects/cpu_0/nexys2.vhd
+++ b/projects/cpu_0/nexys2.vhd
@@ -81,43 +81,23 @@ architecture behavioral of nexys2 is
 	signal dat_miso:          std_logic_vector(7 downto 0);
 
 	signal mem_cyc:           std_logic;
-	signal mem_stb:           std_logic;
-	signal mem_we:            std_logic;
 	signal mem_ack:           std_logic;
-	signal mem_adr:           std_logic_vector(31 downto 0);
-	signal mem_mosi:          std_logic_vector(7 downto 0);
 	signal mem_miso:          std_logic_vector(7 downto 0);
 
 	signal tile_cyc:          std_logic;
-	signal tile_stb:          std_logic;
-	signal tile_we:           std_logic;
 	signal tile_ack:          std_logic;
-	signal tile_adr:          std_logic_vector(31 downto 0);
-	signal tile_mosi:         std_logic_vector(7 downto 0);
 	signal tile_miso:         std_logic_vector(7 downto 0);
 
 	signal host_cyc:          std_logic;
-	signal host_stb:          std_logic;
-	signal host_we:           std_logic;
 	signal host_ack:          std_logic;
-	signal host_adr:          std_logic_vector(31 downto 0);
-	signal host_mosi:         std_logic_vector(7 downto 0);
 	signal host_miso:         std_logic_vector(7 downto 0);
 
 	signal ps2_cyc:           std_logic;
-	signal ps2_stb:           std_logic;
-	signal ps2_we:            std_logic;
 	signal ps2_ack:           std_logic;
-	signal ps2_adr:           std_logic_vector(31 downto 0);
-	signal ps2_mosi:          std_logic_vector(7 downto 0);
 	signal ps2_miso:          std_logic_vector(7 downto 0);
 
 	signal uart_cyc:          std_logic;
-	signal uart_stb:          std_logic;
-	signal uart_we:           std_logic;
 	signal uart_ack:          std_logic;
-	signal uart_adr:          std_logic_vector(31 downto 0);
-	signal uart_mosi:         std_logic_vector(7 downto 0);
 	signal uart_miso:         std_logic_vector(7 downto 0);
 
 	-- Interrupt signals
@@ -167,7 +147,6 @@ architecture behavioral of nexys2 is
 
 begin
 
-	Led <= mem_miso;
 	e_cpu: entity work.cpu
 		port map (
 			rst_i => d_rst,
@@ -205,111 +184,52 @@ begin
 
 	d_rst <= g_rst or h_rst;
 
-	-- Maybe it would be more understandable if the mapper just produced select
-	-- signals from mask/match/address inputs?  Then each device can and the
-	-- global cyc signal with its own select signal, take the rest of the bus
-	-- signals as they are, produce their own miso+ack, then have a separate mux
-	-- for misos+acks?
-	e_mapper: entity utility.wb_mapper
+	-- Flash: 0x00000000-0x00ffffff
+	-- Ram:   0x01000000-0x01ffffff
+	-- Vbuf:  0x02000000-0x02001fff
+	-- Tiles: 0x02002000-0x02003fff
+	-- Host:  0x02004000-0x02004007
+	-- PS2:   0x02004008-0x0200400f
+	-- UART:  0x02004010-0x02004017
+	e_mapper: entity utility.wb_mapper_a32d8
 		generic map (
-			A_WIDTH => 32,
-			D_WIDTH => 8
+			N => 5
 		)
 		port map (
-			cyc_i   => cyc,
-			stb_i   => stb,
-			we_i    => we,
-			ack_o   => ack,
-			adr_i   => adr,
-			dat_i   => dat_mosi,
-			dat_o   => dat_miso,
-
-			-- Flash: 0x00000000-0x00ffffff
-			-- Ram:   0x01000000-0x01ffffff
-			mask_0  => "00000010000000000000000000000000",
-			match_0 => "00000000000000000000000000000000",
-			cyc_o_0 => mem_cyc,
-			stb_o_0 => mem_stb,
-			we_o_0  => mem_we,
-			ack_i_0 => mem_ack,
-			adr_o_0 => mem_adr,
-			dat_o_0 => mem_mosi,
-			dat_i_0 => mem_miso,
-
-			-- Vbuf:  0x02000000-0x02001fff
-			-- Tiles: 0x02002000-0x02003fff
-			mask_1  => "00000010000000000100000000000000",
-			match_1 => "00000010000000000000000000000000",
-			cyc_o_1 => tile_cyc,
-			stb_o_1 => tile_stb,
-			we_o_1  => tile_we,
-			ack_i_1 => tile_ack,
-			adr_o_1 => tile_adr,
-			dat_o_1 => tile_mosi,
-			dat_i_1 => tile_miso,
-
-			-- Host:  0x02004000-0x02004007
-			mask_2  => "00000010000000000100000000011000",
-			match_2 => "00000010000000000100000000000000",
-			cyc_o_2 => host_cyc,
-			stb_o_2 => host_stb,
-			we_o_2  => host_we,
-			ack_i_2 => host_ack,
-			adr_o_2 => host_adr,
-			dat_o_2 => host_mosi,
-			dat_i_2 => host_miso,
-
-			-- PS2:   0x02004008-0x0200400f
-			mask_3  => "00000010000000000100000000011000",
-			match_3 => "00000010000000000100000000001000",
-			cyc_o_3 => ps2_cyc,
-			stb_o_3 => ps2_stb,
-			we_o_3  => ps2_we,
-			ack_i_3 => ps2_ack,
-			adr_o_3 => ps2_adr,
-			dat_o_3 => ps2_mosi,
-			dat_i_3 => ps2_miso,
-
-			-- UART:  0x02004010-0x02004017
-			mask_4  => "00000010000000000100000000011000",
-			match_4 => "00000010000000000100000000010000",
-			cyc_o_4 => uart_cyc,
-			stb_o_4 => uart_stb,
-			we_o_4  => uart_we,
-			ack_i_4 => uart_ack,
-			adr_o_4 => uart_adr,
-			dat_o_4 => uart_mosi,
-			dat_i_4 => uart_miso,
-
-			mask_5  => "00000000000000000000000000000000",
-			match_5 => "00000000000000000000000000000001",
-			cyc_o_5 => open,
-			stb_o_5 => open,
-			we_o_5  => open,
-			ack_i_5 => '1',
-			adr_o_5 => open,
-			dat_o_5 => open,
-			dat_i_5 => "00000000",
-
-			mask_6  => "00000000000000000000000000000000",
-			match_6 => "00000000000000000000000000000001",
-			cyc_o_6 => open,
-			stb_o_6 => open,
-			we_o_6  => open,
-			ack_i_6 => '1',
-			adr_o_6 => open,
-			dat_o_6 => open,
-			dat_i_6 => "00000000",
-
-			mask_7  => "00000000000000000000000000000000",
-			match_7 => "00000000000000000000000000000001",
-			cyc_o_7 => open,
-			stb_o_7 => open,
-			we_o_7  => open,
-			ack_i_7 => '1',
-			adr_o_7 => open,
-			dat_o_7 => open,
-			dat_i_7 => "00000000"
+			cyc_i    => cyc,
+			ack_o    => ack,
+			adr_i    => adr,
+			dat_o    => dat_miso,
+
+			mask(0)  => "00000010000000000000000000000000",
+			mask(1)  => "00000010000000000100000000000000",
+			mask(2)  => "00000010000000000100000000011000",
+			mask(3)  => "00000010000000000100000000011000",
+			mask(4)  => "00000010000000000100000000011000",
+
+			match(0) => "00000000000000000000000000000000",
+			match(1) => "00000010000000000000000000000000",
+			match(2) => "00000010000000000100000000000000",
+			match(3) => "00000010000000000100000000001000",
+			match(4) => "00000010000000000100000000010000",
+
+			cyc_o(0) => mem_cyc,
+			cyc_o(1) => tile_cyc,
+			cyc_o(2) => host_cyc,
+			cyc_o(3) => ps2_cyc,
+			cyc_o(4) => uart_cyc,
+
+			ack_i(0) => mem_ack,
+			ack_i(1) => tile_ack,
+			ack_i(2) => host_ack,
+			ack_i(3) => ps2_ack,
+			ack_i(4) => uart_ack,
+
+			dat_i(0) => mem_miso,
+			dat_i(1) => tile_miso,
+			dat_i(2) => host_miso,
+			dat_i(3) => ps2_miso,
+			dat_i(4) => uart_miso
 		);
 
 
@@ -320,11 +240,11 @@ begin
 
 			-- Internal access
 			cyc_i       => mem_cyc,
-			stb_i       => mem_stb,
-			we_i        => mem_we,
+			stb_i       => stb,
+			we_i        => we,
 			ack_o       => mem_ack,
-			adr_i       => mem_adr(24 downto 0),
-			dat_i       => mem_mosi,
+			adr_i       => adr(24 downto 0),
+			dat_i       => dat_mosi,
 			dat_o       => mem_miso,
 
 			-- Configuration
@@ -356,11 +276,11 @@ begin
 
 			-- Internal access to screen buffer and tile set
 			cyc_i    => tile_cyc,
-			stb_i    => tile_stb,
-			we_i     => tile_we,
+			stb_i    => stb,
+			we_i     => we,
 			ack_o    => tile_ack,
-			adr_i    => tile_adr(13 downto 0),
-			dat_i    => tile_mosi,
+			adr_i    => adr(13 downto 0),
+			dat_i    => dat_mosi,
 			dat_o    => tile_miso,
 
 			-- External pins
@@ -386,11 +306,11 @@ begin
 
 			-- Internal access to control registers
 			d_cyc_i      => host_cyc,
-			d_stb_i      => host_stb,
-			d_we_i       => host_we,
+			d_stb_i      => stb,
+			d_we_i       => we,
 			d_ack_o      => host_ack,
-			d_adr_i      => host_adr(2 downto 0),
-			d_dat_i      => host_mosi,
+			d_adr_i      => adr(2 downto 0),
+			d_dat_i      => dat_mosi,
 			d_dat_o      => host_miso,
 
 			-- Internal memory interface, can be switched off to allow the host to control memory
@@ -435,7 +355,7 @@ begin
 			seg          => seg,
 			dp           => dp,
 			an           => an,
-			Led          => open,
+			Led          => Led,
 			sw           => sw
 		);
 
@@ -457,11 +377,11 @@ begin
 
 			-- Internal access
 			cyc_i       => ps2_cyc,
-			stb_i       => ps2_stb,
-			we_i        => ps2_we,
+			stb_i       => stb,
+			we_i        => we,
 			ack_o       => ps2_ack,
-			adr_i       => ps2_adr(2 downto 0),
-			dat_i       => ps2_mosi,
+			adr_i       => adr(2 downto 0),
+			dat_i       => dat_mosi,
 			dat_o       => ps2_miso,
 
 			-- Interrupt signals
@@ -496,11 +416,11 @@ begin
 
 			-- Internal access
 			cyc_i        => uart_cyc,
-			stb_i        => uart_stb,
-			we_i         => uart_we,
+			stb_i        => stb,
+			we_i         => we,
 			ack_o        => uart_ack,
-			adr_i        => uart_adr(2 downto 0),
-			dat_i        => uart_mosi,
+			adr_i        => adr(2 downto 0),
+			dat_i        => dat_mosi,
 			dat_o        => uart_miso,
 
 			-- Interrupt signals