From: Ryan <>
Date: Wed, 17 Sep 2025 21:46:29 +0000 (-0500)
Subject: Update hardware test for nexys2 memctrl
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=bb0632e4f84a47301fa48c6101b9996d28df472f;p=vhdl

Update hardware test for nexys2 memctrl
---

diff --git a/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd b/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
index 1abd80d..a8d824f 100644
--- a/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
+++ b/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
@@ -82,7 +82,7 @@ architecture behavioral of test_nexys2_mem_wb8_0 is
 begin
 
 	mem_adr <= "000000000000000000" & adr(5 downto 0);
-	e_mem: entity work.mem_wb8_0
+	e_mem: entity work.mem_wb8_0_opt
 		port map (
 			rst_i       => rst,
 			clk_i       => clk,
@@ -96,7 +96,7 @@ begin
 			dat_i       => dat_mosi,
 			dat_o       => mem_miso,
 
-			wait_cycles => temp(4 downto 0),
+			--wait_cycles => temp(4 downto 0),
 
 			MemOE       => d_MemOE,
 			MemWR       => d_MemWR,