From: rs <>
Date: Fri, 12 Dec 2025 03:09:24 +0000 (-0600)
Subject: Allow interstage register of zero width
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=b7309341a4796ce6742ebea18e05cfd443edf29b;p=vhdl

Allow interstage register of zero width
---

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index cde4634..39b55e4 100644
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -4,7 +4,7 @@ use ieee.std_logic_1164.all;
 
 entity pipectrl is
 	generic (
-		WIDTH: positive := 16
+		WIDTH: natural := 16
 	);
 	port (
 		rst_i: in  std_logic;
@@ -14,7 +14,7 @@ entity pipectrl is
 
 		stb_i: in  std_logic;
 		rdy_o: out std_logic;
-		dat_i: in  std_logic_vector(WIDTH-1 downto 0);
+		dat_i: in  std_logic_vector(WIDTH-1 downto 0) := (others => '0');
 
 		stb_o: out std_logic;
 		rdy_i: in  std_logic;