From: rs <> Date: Wed, 12 Nov 2025 05:18:27 +0000 (-0600) Subject: Make naming convention more consistent X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=8d0e816bbbe9c492c062588b506908781ff62b4d;p=vhdl Make naming convention more consistent --- diff --git a/libraries/nexys2/tests/nexys2_usb.vhd b/libraries/nexys2/tests/nexys2_usb.vhd index c8e4816..ec02f8c 100644 --- a/libraries/nexys2/tests/nexys2_usb.vhd +++ b/libraries/nexys2/tests/nexys2_usb.vhd @@ -56,7 +56,7 @@ begin rst_o => rst ); - e_usb: entity work.usb_cypress + e_usb: entity work.usb port map ( rst_i => rst, diff --git a/libraries/nexys2/usb.vhd b/libraries/nexys2/usb.vhd index 8a0956b..e6e0829 100644 --- a/libraries/nexys2/usb.vhd +++ b/libraries/nexys2/usb.vhd @@ -6,7 +6,7 @@ library utility; library work; -entity usb_cypress is +entity usb is generic (SYNC_STAGES: positive := 2); port ( rst_i: in std_logic; @@ -48,10 +48,10 @@ entity usb_cypress is stm_ul_ack_o: out std_logic; stm_ul_dat_i: in std_logic_vector(7 downto 0) ); -end usb_cypress; +end usb; -architecture behavioral of usb_cypress is +architecture behavioral of usb is signal ifclk_rst: std_logic; signal epp_rst: std_logic; @@ -68,14 +68,14 @@ architecture behavioral of usb_cypress is signal epp_wait: std_logic; -- Between USB mux and EPP interface, in epp_clk_i domain - signal xclk_eppen: std_logic; - signal xclk_astb: std_logic; - signal xclk_dstb: std_logic; - signal xclk_write: std_logic; - signal xclk_db_i: std_logic_vector(7 downto 0); - signal xclk_db_o: std_logic_vector(7 downto 0); - signal xclk_db_w: std_logic; - signal xclk_wait: std_logic; + signal sync_eppen: std_logic; + signal sync_astb: std_logic; + signal sync_dstb: std_logic; + signal sync_write: std_logic; + signal sync_db_i: std_logic_vector(7 downto 0); + signal sync_db_o: std_logic_vector(7 downto 0); + signal sync_db_w: std_logic; + signal sync_wait: std_logic; -- Between USB mux and STM interface signal dstm_ifclk: std_logic; @@ -176,58 +176,58 @@ begin -- EPP Interface -- EPP clock domain crossing - e_xclk_eppen: entity utility.sync_sig + e_sync_eppen: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES, INIT => '0') port map ( rst_i => epp_rst, clk_i => epp_clk_i, sig_i => epp_en, - sig_o => xclk_eppen + sig_o => sync_eppen ); - e_xclk_astb: entity utility.sync_sig + e_sync_astb: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => epp_clk_i, sig_i => epp_astb, - sig_o => xclk_astb + sig_o => sync_astb ); - e_xclk_dstb: entity utility.sync_sig + e_sync_dstb: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES) port map ( clk_i => epp_clk_i, sig_i => epp_dstb, - sig_o => xclk_dstb + sig_o => sync_dstb ); - e_xclk_wait: entity utility.sync_sig + e_sync_wait: entity utility.sync_sig generic map (SYNC_STAGES => SYNC_STAGES, INIT => '0') -- FIXME: is this the best initial value for WAIT? port map ( rst_i => ifclk_rst, clk_i => DstmIFCLK, - sig_i => xclk_wait, + sig_i => sync_wait, sig_o => epp_wait ); -- These signals are stable during the time that they're validated by the -- synchronized handshaking signals, so no clock synchronizing is needed - xclk_write <= epp_write; - xclk_db_i <= epp_db_i; - epp_db_o <= xclk_db_o; - epp_db_w <= xclk_db_w; + sync_write <= epp_write; + sync_db_i <= epp_db_i; + epp_db_o <= sync_db_o; + epp_db_w <= sync_db_w; -- EPP interface logic e_epp: entity work.eppex_wb port map ( - EppEN => xclk_eppen, - EppAstb => xclk_astb, - EppDstb => xclk_dstb, - EppWr => xclk_write, - EppDB_i => xclk_db_i, - EppDB_o => xclk_db_o, - EppDB_w => xclk_db_w, - EppWait => xclk_wait, + EppEN => sync_eppen, + EppAstb => sync_astb, + EppDstb => sync_dstb, + EppWr => sync_write, + EppDB_i => sync_db_i, + EppDB_o => sync_db_o, + EppDB_w => sync_db_w, + EppWait => sync_wait, rst_i => epp_rst, clk_i => epp_clk_i, @@ -270,7 +270,7 @@ begin ); -- STM clock domain crossing, download side - e_dl_fifo: entity utility.fifo_xclk + e_dl_fifo: entity utility.sync_fifo_2k_8 generic map (SYNC_STAGES => SYNC_STAGES) port map ( head_rst_i => ifclk_rst, @@ -287,7 +287,7 @@ begin ); -- STM clock domain crossing, upload side - e_ul_fifo: entity utility.fifo_xclk + e_ul_fifo: entity utility.sync_fifo_2k_8 generic map (SYNC_STAGES => SYNC_STAGES) port map ( head_rst_i => stm_rst, diff --git a/libraries/utility/fifo_xclk.vhd b/libraries/utility/fifo_xclk.vhd deleted file mode 100644 index 7ade367..0000000 --- a/libraries/utility/fifo_xclk.vhd +++ /dev/null @@ -1,181 +0,0 @@ --------------------------------------------------------------------------------- --- fifo_xclk - cross clock domain FIFO --- --- Generics: --- SYNC_STAGES - number of shift register stages to use when synchronizing --- --- Ports: --- head_rst_i - synchronous reset in head clock domain --- head_clk_i - clock domain for data insertion --- head_stb_i - high to trigger insertion of a byte --- head_rdy_o - high when head can accept bytes --- head_dat_i - byte to insert into the head --- tail_rst_i - synchronous reset in tail clock domain --- tail_clk_i - clock domain for data removal --- tail_stb_o - high when a byte is available for removal --- tail_ack_i - high to trigger acknowledgement of current tail byte --- tail_dat_o - current tail byte when tail_stb_o is asserted --- --- The head and tail reset are only separate to prevent duplication of reset --- synchronization logic. Both ends should always be reset together, although --- it is acceptable for one end to come out of reset before the other due to --- differences in clock rates. --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -library utility; - - -entity fifo_xclk is - generic (SYNC_STAGES: positive := 2); - port ( - head_rst_i: in std_logic; - head_clk_i: in std_logic; - head_stb_i: in std_logic; - head_rdy_o: out std_logic; - head_dat_i: in std_logic_vector(7 downto 0); - - tail_rst_i: in std_logic; - tail_clk_i: in std_logic; - tail_stb_o: out std_logic; - tail_ack_i: in std_logic; - tail_dat_o: out std_logic_vector(7 downto 0) - ); -end fifo_xclk; - - -architecture behavioral of fifo_xclk is - - signal head_rst_wait: std_logic; - signal tail_adr_xclk: std_logic_vector(10 downto 0); - signal head_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); - signal head_adr_next: std_logic_vector(10 downto 0); - signal head_rdy: std_logic; - signal head_step: std_logic; - signal is_full: std_logic; - - signal tail_rst_wait: std_logic; - signal head_adr_xclk: std_logic_vector(10 downto 0); - signal tail_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); - signal tail_adr_inc: std_logic_vector(10 downto 0); - signal tail_adr_next: std_logic_vector(10 downto 0); - signal tail_stb: std_logic; - signal tail_step: std_logic; - signal is_empty: std_logic; - -begin - - -- Head logic - - e_sync_tail_rst: entity utility.sync_sig - generic map (SYNC_STAGES => SYNC_STAGES) - port map ( - clk_i => head_clk_i, - sig_i => tail_rst_i, - sig_o => head_rst_wait - ); - - e_xclk_tail: entity utility.sync_vec - generic map (SYNC_STAGES => SYNC_STAGES) - port map ( - clk_i => head_clk_i, - sig_i => std_logic_vector(tail_adr_reg), - sig_o => tail_adr_xclk - ); - - is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_xclk or - head_rst_i = '1' or head_rst_wait = '1' - else '0'; - - head_rdy <= not is_full; - head_rdy_o <= head_rdy; - - head_step <= head_stb_i and head_rdy; - - e_head_adr: entity utility.gray_counter - generic map (N => 11) - port map ( - rst_i => head_rst_i, - clk_i => head_clk_i, - ena_i => head_step, - gray => head_adr_reg, - inc => head_adr_next - ); - - - -- Tail logic - - e_sync_head_rst: entity utility.sync_sig - generic map (SYNC_STAGES => SYNC_STAGES) - port map ( - clk_i => tail_clk_i, - sig_i => head_rst_i, - sig_o => tail_rst_wait - ); - - e_xclk_head: entity utility.sync_vec - generic map (SYNC_STAGES => SYNC_STAGES) - port map ( - clk_i => tail_clk_i, - sig_i => std_logic_vector(head_adr_reg), - sig_o => head_adr_xclk - ); - - is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_xclk or - tail_rst_i = '1' or tail_rst_wait = '1' - else '0'; - - tail_stb <= not is_empty; - tail_stb_o <= tail_stb; - - tail_step <= tail_stb and tail_ack_i; - tail_adr_next <= tail_adr_inc when tail_step = '1' else tail_adr_reg; - - e_tail_adr: entity utility.gray_counter - generic map (N => 11) - port map ( - rst_i => tail_rst_i, - clk_i => tail_clk_i, - ena_i => tail_step, - gray => tail_adr_reg, - inc => tail_adr_inc - ); - - - -- FIFO memory - - e_fifo: ramb16_s9_s9 - generic map ( - SIM_COLLISION_CHECK => "GENERATE_X_ONLY" - ) - port map ( - -- Port A is the FIFO head - wea => head_step, - ena => '1', - ssra => '0', - clka => head_clk_i, - addra => std_logic_vector(head_adr_reg), - dia => head_dat_i, - dipa => "0", - doa => open, - dopa => open, - - -- Port B is the FIFO tail - web => '0', - enb => '1', - ssrb => '0', - clkb => tail_clk_i, - addrb => std_logic_vector(tail_adr_next), - dib => x"00", - dipb => "0", - dob => tail_dat_o, - dopb => open - ); - -end behavioral; diff --git a/libraries/utility/sync_fifo_2k_8.vhd b/libraries/utility/sync_fifo_2k_8.vhd new file mode 100644 index 0000000..f571922 --- /dev/null +++ b/libraries/utility/sync_fifo_2k_8.vhd @@ -0,0 +1,181 @@ +-------------------------------------------------------------------------------- +-- sync_fifo_2k_8 - cross clock domain FIFO, 2048x8-bit +-- +-- Generics: +-- SYNC_STAGES - number of shift register stages to use when synchronizing +-- +-- Ports: +-- head_rst_i - synchronous reset in head clock domain +-- head_clk_i - clock domain for data insertion +-- head_stb_i - high to trigger insertion of a byte +-- head_rdy_o - high when head can accept bytes +-- head_dat_i - byte to insert into the head +-- tail_rst_i - synchronous reset in tail clock domain +-- tail_clk_i - clock domain for data removal +-- tail_stb_o - high when a byte is available for removal +-- tail_ack_i - high to trigger acknowledgement of current tail byte +-- tail_dat_o - current tail byte when tail_stb_o is asserted +-- +-- The head and tail reset are only separate to prevent duplication of reset +-- synchronization logic. Both ends should always be reset together, although +-- it is acceptable for one end to come out of reset before the other due to +-- differences in clock rates. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library utility; + + +entity sync_fifo_2k_8 is + generic (SYNC_STAGES: positive := 2); + port ( + head_rst_i: in std_logic; + head_clk_i: in std_logic; + head_stb_i: in std_logic; + head_rdy_o: out std_logic; + head_dat_i: in std_logic_vector(7 downto 0); + + tail_rst_i: in std_logic; + tail_clk_i: in std_logic; + tail_stb_o: out std_logic; + tail_ack_i: in std_logic; + tail_dat_o: out std_logic_vector(7 downto 0) + ); +end sync_fifo_2k_8; + + +architecture behavioral of sync_fifo_2k_8 is + + signal head_rst_wait: std_logic; + signal tail_adr_sync: std_logic_vector(10 downto 0); + signal head_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); + signal head_adr_next: std_logic_vector(10 downto 0); + signal head_rdy: std_logic; + signal head_step: std_logic; + signal is_full: std_logic; + + signal tail_rst_wait: std_logic; + signal head_adr_sync: std_logic_vector(10 downto 0); + signal tail_adr_reg: std_logic_vector(10 downto 0) := (others => '0'); + signal tail_adr_inc: std_logic_vector(10 downto 0); + signal tail_adr_next: std_logic_vector(10 downto 0); + signal tail_stb: std_logic; + signal tail_step: std_logic; + signal is_empty: std_logic; + +begin + + -- Head logic + + e_sync_tail_rst: entity utility.sync_sig + generic map (SYNC_STAGES => SYNC_STAGES) + port map ( + clk_i => head_clk_i, + sig_i => tail_rst_i, + sig_o => head_rst_wait + ); + + e_sync_tail: entity utility.sync_vec + generic map (SYNC_STAGES => SYNC_STAGES) + port map ( + clk_i => head_clk_i, + sig_i => std_logic_vector(tail_adr_reg), + sig_o => tail_adr_sync + ); + + is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_sync or + head_rst_i = '1' or head_rst_wait = '1' + else '0'; + + head_rdy <= not is_full; + head_rdy_o <= head_rdy; + + head_step <= head_stb_i and head_rdy; + + e_head_adr: entity utility.gray_counter + generic map (N => 11) + port map ( + rst_i => head_rst_i, + clk_i => head_clk_i, + ena_i => head_step, + gray => head_adr_reg, + inc => head_adr_next + ); + + + -- Tail logic + + e_sync_head_rst: entity utility.sync_sig + generic map (SYNC_STAGES => SYNC_STAGES) + port map ( + clk_i => tail_clk_i, + sig_i => head_rst_i, + sig_o => tail_rst_wait + ); + + e_sync_head: entity utility.sync_vec + generic map (SYNC_STAGES => SYNC_STAGES) + port map ( + clk_i => tail_clk_i, + sig_i => std_logic_vector(head_adr_reg), + sig_o => head_adr_sync + ); + + is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_sync or + tail_rst_i = '1' or tail_rst_wait = '1' + else '0'; + + tail_stb <= not is_empty; + tail_stb_o <= tail_stb; + + tail_step <= tail_stb and tail_ack_i; + tail_adr_next <= tail_adr_inc when tail_step = '1' else tail_adr_reg; + + e_tail_adr: entity utility.gray_counter + generic map (N => 11) + port map ( + rst_i => tail_rst_i, + clk_i => tail_clk_i, + ena_i => tail_step, + gray => tail_adr_reg, + inc => tail_adr_inc + ); + + + -- FIFO memory + + e_fifo: ramb16_s9_s9 + generic map ( + SIM_COLLISION_CHECK => "GENERATE_X_ONLY" + ) + port map ( + -- Port A is the FIFO head + wea => head_step, + ena => '1', + ssra => '0', + clka => head_clk_i, + addra => std_logic_vector(head_adr_reg), + dia => head_dat_i, + dipa => "0", + doa => open, + dopa => open, + + -- Port B is the FIFO tail + web => '0', + enb => '1', + ssrb => '0', + clkb => tail_clk_i, + addrb => std_logic_vector(tail_adr_next), + dib => x"00", + dipb => "0", + dob => tail_dat_o, + dopb => open + ); + +end behavioral;