From: rs <>
Date: Tue, 11 Nov 2025 22:32:55 +0000 (-0600)
Subject: Remove unnecessary clock synchronization
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=78f890c2667fa7c239aca4bb762a192697d93729;p=vhdl

Remove unnecessary clock synchronization
---

diff --git a/libraries/nexys2/usb.vhd b/libraries/nexys2/usb.vhd
index 5ae0966..878dbd0 100644
--- a/libraries/nexys2/usb.vhd
+++ b/libraries/nexys2/usb.vhd
@@ -143,8 +143,6 @@ begin
 	-- EPP Interface
 
 	-- EPP clock domain crossing
-	-- Both ends are handshaken, but this end has fewer signals to cross
-	-- FIXME: it should only be necessary to synchronize the handshaking signals
 	e_xclk_eppen: entity utility.xclk_sig
 		generic map (INIT => '0')
 		port map (a_sig_i => epp_en,    b_clk_i => epp_clk_i, b_sig_o => xclk_eppen);
@@ -157,24 +155,17 @@ begin
 		generic map (INIT => '1')
 		port map (a_sig_i => epp_dstb,  b_clk_i => epp_clk_i, b_sig_o => xclk_dstb);
 
-	e_xclk_write: entity utility.xclk_sig
-		generic map (INIT => '1')
-		port map (a_sig_i => epp_write, b_clk_i => epp_clk_i, b_sig_o => xclk_write);
-
-	e_xclk_db_i: entity utility.xclk_vec
-		port map (a_sig_i => epp_db_i,  b_clk_i => epp_clk_i, b_sig_o => xclk_db_i);
-
-	e_xclk_db_o: entity utility.xclk_vec
-		port map (a_sig_i => xclk_db_o, b_clk_i => DstmIFCLK, b_sig_o => epp_db_o);
-
-	e_xclk_db_w: entity utility.xclk_sig
-		generic map (INIT => '0')
-		port map (a_sig_i => xclk_db_w, b_clk_i => DstmIFCLK, b_sig_o => epp_db_w);
-
 	e_xclk_wait: entity utility.xclk_sig
 		generic map (INIT => '0')  -- FIXME: is this the best initial value for WAIT?
 		port map (a_sig_i => xclk_wait, b_clk_i => DstmIFCLK, b_sig_o => epp_wait);
 
+	-- These signals are stable during the time that they're validated by the
+	-- synchronized handshaking signals, so no clock synchronizing is needed
+	xclk_write <= epp_write;
+	xclk_db_i  <= epp_db_i;
+	epp_db_o   <= xclk_db_o;
+	epp_db_w   <= xclk_db_w;
+
 	-- EPP interface logic
 	e_epp: entity work.eppex_wb
 		port map (