From: Ryan <>
Date: Tue, 30 Sep 2025 07:47:43 +0000 (-0500)
Subject: Switch full-system sim test to latest CPU0
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=4c32c9fd4564c960a8d74225cd6f587dc927f95d;p=vhdl

Switch full-system sim test to latest CPU0
---

diff --git a/projects/cpu_0/tests/test_nexys2.vhd b/projects/cpu_0/tests/test_nexys2.vhd
index d8010b2..396fde2 100644
--- a/projects/cpu_0/tests/test_nexys2.vhd
+++ b/projects/cpu_0/tests/test_nexys2.vhd
@@ -82,6 +82,7 @@ begin
 	flash_ce <= "00" & FlashCS;
 	flash_adr <= MemAdr & '0';
 	e_flash: entity simulated.js28f128j3d75
+		generic map (FILENAME => "/home/ryan/Dropbox/Projects/VHDL/projects/cpu_0/asm/int_test2.bin")
 		port map (
 			a      => flash_adr,
 			d      => MemDB,
@@ -111,7 +112,7 @@ begin
 		);
 
 
-	e_uut: entity work.nexys2
+	e_uut: entity work.nexys2_speed
 		port map (
 			clk_50     => clk_50,
 			DB         => DB,