From: rs <>
Date: Fri, 19 Sep 2025 04:26:35 +0000 (-0500)
Subject: Add clock enable to seven-seg-mux
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=3014b3757ad694a381e7b081f0964eb1111165bd;p=vhdl

Add clock enable to seven-seg-mux
---

diff --git a/libraries/nexys2/host_regs.vhd b/libraries/nexys2/host_regs.vhd
index ab56e95..e47af8f 100644
--- a/libraries/nexys2/host_regs.vhd
+++ b/libraries/nexys2/host_regs.vhd
@@ -159,6 +159,7 @@ begin
 	e_seven_seg_mux: entity work.seven_seg_mux
 		port map (
 			clk_in   => clk_div(15),
+			clk_en   => '1',
 
 			seg_0_in => regs(4)(6 downto 0),
 			seg_1_in => regs(5)(6 downto 0),
diff --git a/libraries/nexys2/seven_seg_mux.vhd b/libraries/nexys2/seven_seg_mux.vhd
index c2d56cd..8ecfe06 100644
--- a/libraries/nexys2/seven_seg_mux.vhd
+++ b/libraries/nexys2/seven_seg_mux.vhd
@@ -10,6 +10,7 @@ use ieee.numeric_std.all;
 entity seven_seg_mux is
 	port (
 		clk_in:   in  std_logic;
+		clk_en:   in  std_logic;
 
 		seg_0_in: in  std_logic_vector(6 downto 0);
 		seg_1_in: in  std_logic_vector(6 downto 0);
@@ -32,7 +33,7 @@ begin
 
 	process(clk_in)
 	begin
-		if rising_edge(clk_in) then
+		if rising_edge(clk_in) and clk_en = '1' then
 			an_reg <= an_reg + 1;
 		end if;
 	end process;