From: rs <>
Date: Wed, 12 Nov 2025 04:59:17 +0000 (-0600)
Subject: Stall synching FIFO until both ends leave reset
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=2fc525b70a0ce9f4c0b85feca46e2c86af1cd6f3;p=vhdl

Stall synching FIFO until both ends leave reset
---

diff --git a/libraries/utility/fifo_xclk.vhd b/libraries/utility/fifo_xclk.vhd
index 3254cd2..7ade367 100644
--- a/libraries/utility/fifo_xclk.vhd
+++ b/libraries/utility/fifo_xclk.vhd
@@ -52,7 +52,7 @@ end fifo_xclk;
 
 architecture behavioral of fifo_xclk is
 
-	signal head_rst:      std_logic;
+	signal head_rst_wait: std_logic;
 	signal tail_adr_xclk: std_logic_vector(10 downto 0);
 	signal head_adr_reg:  std_logic_vector(10 downto 0) := (others => '0');
 	signal head_adr_next: std_logic_vector(10 downto 0);
@@ -60,7 +60,7 @@ architecture behavioral of fifo_xclk is
 	signal head_step:     std_logic;
 	signal is_full:       std_logic;
 
-	signal tail_rst:      std_logic;
+	signal tail_rst_wait: std_logic;
 	signal head_adr_xclk: std_logic_vector(10 downto 0);
 	signal tail_adr_reg:  std_logic_vector(10 downto 0) := (others => '0');
 	signal tail_adr_inc:  std_logic_vector(10 downto 0);
@@ -73,6 +73,14 @@ begin
 
 	-- Head logic
 
+	e_sync_tail_rst: entity utility.sync_sig
+		generic map (SYNC_STAGES => SYNC_STAGES)
+		port map (
+			clk_i => head_clk_i,
+			sig_i => tail_rst_i,
+			sig_o => head_rst_wait
+		);
+
 	e_xclk_tail: entity utility.sync_vec
 		generic map (SYNC_STAGES => SYNC_STAGES)
 		port map (
@@ -81,7 +89,9 @@ begin
 			sig_o => tail_adr_xclk
 		);
 
-	is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_xclk else '0';
+	is_full <= '1' when std_logic_vector(head_adr_next) = tail_adr_xclk or
+	                    head_rst_i = '1' or head_rst_wait = '1'
+	               else '0';
 
 	head_rdy <= not is_full;
 	head_rdy_o <= head_rdy;
@@ -101,6 +111,14 @@ begin
 
 	-- Tail logic
 
+	e_sync_head_rst: entity utility.sync_sig
+		generic map (SYNC_STAGES => SYNC_STAGES)
+		port map (
+			clk_i => tail_clk_i,
+			sig_i => head_rst_i,
+			sig_o => tail_rst_wait
+		);
+
 	e_xclk_head: entity utility.sync_vec
 		generic map (SYNC_STAGES => SYNC_STAGES)
 		port map (
@@ -109,7 +127,9 @@ begin
 			sig_o => head_adr_xclk
 		);
 
-	is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_xclk else '0';
+	is_empty <= '1' when std_logic_vector(tail_adr_reg) = head_adr_xclk or
+	                     tail_rst_i = '1' or tail_rst_wait = '1'
+	                else '0';
 
 	tail_stb <= not is_empty;
 	tail_stb_o <= tail_stb;