From: Ryan <>
Date: Fri, 3 Oct 2025 00:57:02 +0000 (-0500)
Subject: Adjust VGA vert timing and change sync polarity
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=2f1e2fe1d56117a72995d1f71e543f5b688a3f54;p=vhdl

Adjust VGA vert timing and change sync polarity
---

diff --git a/libraries/vga/vga_counter.vhd b/libraries/vga/vga_counter.vhd
index 8f3d400..b7ae868 100644
--- a/libraries/vga/vga_counter.vhd
+++ b/libraries/vga/vga_counter.vhd
@@ -22,7 +22,7 @@ entity vga_counter is
 		V_DISPLAY:     integer := 480;
 		V_FRONT_PORCH: integer := 10;
 		V_SYNC_WIDTH:  integer := 2;
-		V_BACK_PORCH:  integer := 29
+		V_BACK_PORCH:  integer := 33
 	);
 	port (
 		clk_50:  in  std_logic;
@@ -114,9 +114,9 @@ begin
 	begin
 		if rising_edge(clk_50) then
 			if h_sync_start = '1' then
-				h_sync_reg <= '1';
-			elsif h_sync_end = '1' then
 				h_sync_reg <= '0';
+			elsif h_sync_end = '1' then
+				h_sync_reg <= '1';
 			end if;
 		end if;
 	end process;
@@ -160,9 +160,9 @@ begin
 	begin
 		if rising_edge(clk_50) then
 			if v_sync_start = '1' then
-				v_sync_reg <= '1';
-			elsif v_sync_end = '1' then
 				v_sync_reg <= '0';
+			elsif v_sync_end = '1' then
+				v_sync_reg <= '1';
 			end if;
 		end if;
 	end process;