From: rs <>
Date: Tue, 11 Nov 2025 20:44:17 +0000 (-0600)
Subject: Add gate input to assert_setuphold
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=1c10a7a0a3452152cc2bd56ee1d062e6c5163c6e;p=vhdl

Add gate input to assert_setuphold
---

diff --git a/libraries/simulated/util_assert_setuphold.vhd b/libraries/simulated/util_assert_setuphold.vhd
index 664d165..2bd2c34 100644
--- a/libraries/simulated/util_assert_setuphold.vhd
+++ b/libraries/simulated/util_assert_setuphold.vhd
@@ -11,8 +11,9 @@ entity assert_setuphold is
 		NAME_SIG: string    := "<sig>"
 	);
 	port (
-		ref: in std_logic;  -- Reference signal for setup/hold times, e.g. clock
-		sig: in std_logic
+		ref:  in std_logic;  -- Reference signal for setup/hold times, e.g. clock
+		sig:  in std_logic;
+		gate: in std_logic := '1'  -- Set to 1 when edges should be checked - for when setup time is greater than clock period
 	);
 end assert_setuphold;
 
@@ -42,7 +43,7 @@ begin
 			end if;
 
 			-- Check setup time constraint unless this is the beginning of the simulation
-			if now > 0 ps then
+			if now > 0 ps and gate = '1' then
 				assert setup_time >= T_SETUP
 					report "Setup time to '" & NAME_REF & "' <= " & std_logic'image(LEVEL) & " violation for " & NAME_SIG &
 					       " (actual: " & time'image(setup_time) & ", required: " & time'image(T_SETUP) & ")"
@@ -51,7 +52,7 @@ begin
 		end if;
 
 		-- Detect changes in "sig" but only if "ref" has had an edge before
-		if sig'event and last_edge > 0 ps then
+		if sig'event and last_edge > 0 ps and gate = '1' then
 			-- Checking against ref'last_event is tempting, but it might catch the wrong kind of transition
 			hold_time := now - last_edge;
 
diff --git a/libraries/simulated/util_assert_setuphold_vec.vhd b/libraries/simulated/util_assert_setuphold_vec.vhd
index e362d4b..e6f3ede 100644
--- a/libraries/simulated/util_assert_setuphold_vec.vhd
+++ b/libraries/simulated/util_assert_setuphold_vec.vhd
@@ -11,8 +11,9 @@ entity assert_setuphold_vec is
 		NAME_SIG: string    := "<sig>"
 	);
 	port (
-		ref: in std_logic;  -- Reference signal for setup/hold times, e.g. clock
-		sig: in std_logic_vector
+		ref:  in std_logic;  -- Reference signal for setup/hold times, e.g. clock
+		sig:  in std_logic_vector;
+		gate: in std_logic := '1'  -- Set to 1 when edges should be checked - for when setup time is greater than clock period
 	);
 end assert_setuphold_vec;
 
@@ -42,7 +43,7 @@ begin
 			end if;
 
 			-- Check setup time constraint unless this is the beginning of the simulation
-			if now > 0 ps then
+			if now > 0 ps and gate = '1' then
 				assert setup_time >= T_SETUP
 				    report "Setup time to '" & NAME_REF & "' <= " & std_logic'image(LEVEL) & " violation for " & NAME_SIG &
 				           " (actual: " & time'image(setup_time) & ", required: " & time'image(T_SETUP) & ")"
@@ -51,7 +52,7 @@ begin
 		end if;
 
 		-- Detect changes in "sig" but only if "ref" has had an edge before
-		if sig'event and last_edge > 0 ps then
+		if sig'event and last_edge > 0 ps and gate = '1' then
 			-- Checking against ref'last_event is tempting, but it might catch the wrong kind of transition
 			hold_time := now - last_edge;