From: Ryan <>
Date: Tue, 30 Sep 2025 07:38:09 +0000 (-0500)
Subject: Add default output reg value to jtag for sims
X-Git-Url: https://git.the-white-hart.net/?a=commitdiff_plain;h=10c07ca1d7f68f8cbbcc5037f39025f4e254b2a0;p=vhdl

Add default output reg value to jtag for sims
---

diff --git a/libraries/utility/jtag_reg.vhd b/libraries/utility/jtag_reg.vhd
index 69e3da4..0b4814a 100644
--- a/libraries/utility/jtag_reg.vhd
+++ b/libraries/utility/jtag_reg.vhd
@@ -30,7 +30,7 @@ architecture behavioral of jtag_reg is
 	signal update_cross_reg: std_logic_vector(3 downto 0);
 
 	signal shift_reg:  std_logic_vector(N-1 downto 0);
-	signal outbuf_reg: std_logic_vector(N-1 downto 0);
+	signal outbuf_reg: std_logic_vector(N-1 downto 0) := (others => '0');
 
 begin