Add negative-on-reset counter experiment

diff --git a/projects/experimental/rstcount.vhd b/projects/experimental/rstcount.vhd
new file mode 100644 (file)
index 0000000..2b99882
--- /dev/null
+++ b/projects/experimental/rstcount.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity rstcount is
+       port (
+               rst_i: in  std_logic;
+               clk_i: in  std_logic;
+
+               dat_o: out std_logic_vector(8 downto 0)
+       );
+end rstcount;
+
+
+architecture behavioral of rstcount is
+
+       signal count: signed(8 downto 0);
+
+begin
+
+       dat_o <= std_logic_vector(count);
+
+       -- Normal 9-bit counter for reference
+       -- Slice FFs:  9
+       -- Occupied:   5
+       -- Total LUTs: 9
+       --process (rst_i, clk_i, count)
+       --begin
+       --      if rising_edge(clk_i) then
+       --              if rst_i = '1' then
+       --                      count <= "111111000";
+       --              else
+       --                      count <= count + 1;
+       --              end if;
+       --      end if;
+       --end process;
+
+       -- Counter where upper bit gets stuck at zero when not in reset
+       -- Not much worse, looks like a fine design
+       -- Slice FFs:  9
+       -- Occupied:   6
+       -- Total LUTs: 10
+       process (rst_i, clk_i, count)
+               variable x: std_logic;
+       begin
+               if rising_edge(clk_i) then
+                       if rst_i = '1' then
+                               count <= "111111000";
+                       else
+                               x := count(8);
+                               count <= count + 1;
+                               if x = '0' then
+                                       count(8) <= '0';
+                               end if;
+                       end if;
+               end if;
+       end process;
+
+end behavioral;

diff --git a/projects/experimental/tests/test_rstcount.vhd b/projects/experimental/tests/test_rstcount.vhd
new file mode 100644 (file)
index 0000000..9503423
--- /dev/null
+++ b/projects/experimental/tests/test_rstcount.vhd
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+
+
+entity test_rstcount is
+end test_rstcount; 
+
+
+architecture behavior of test_rstcount is
+
+       constant CLK_I_PERIOD: time := 20 ns;
+
+       signal rst_i: std_logic;
+       signal clk_i: std_logic;
+       signal dat_o: std_logic_vector(8 downto 0);
+
+begin
+
+       p_test: process
+       begin
+               -- Reset
+               rst_i <= '1';
+               wait for CLK_I_PERIOD;
+               rst_i <= '0';
+
+               -- Done
+               wait;
+       end process;
+
+       e_uut: entity work.rstcount
+               port map (
+                       rst_i => rst_i,
+                       clk_i => clk_i,
+                       dat_o => dat_o
+               );
+
+       p_clk: process
+       begin
+               clk_i <= '0';
+               wait for CLK_I_PERIOD/2;
+               clk_i <= '1';
+               wait for CLK_I_PERIOD/2;
+       end process;
+
+end;