Add performance testing experiment

diff --git a/projects/experimental/perf.vhd b/projects/experimental/perf.vhd
new file mode 100644 (file)
index 0000000..4003c1a
--- /dev/null
+++ b/projects/experimental/perf.vhd
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity perf is
+       port (
+               clk: in  std_logic;
+               a:   in  std_logic_vector(32 downto 0);
+               b:   in  std_logic_vector(32 downto 0);
+               x:   in  std_logic_vector(32 downto 0);
+               c:   out std_logic_vector(32 downto 0)
+       );
+end perf;
+
+
+architecture behavioral of perf is
+
+       signal a_reg: std_logic_vector(32 downto 0);
+       signal b_reg: std_logic_vector(32 downto 0);
+       signal x_reg: std_logic_vector(32 downto 0);
+       signal c_reg: std_logic_vector(32 downto 0);
+
+begin
+
+       process (clk, a, b)
+       begin
+               if rising_edge(clk) then
+                       a_reg <= a;
+                       b_reg <= b;
+                       x_reg <= x;
+
+                       -- Minimum period: 1.903ns (Maximum Frequency: 525.486MHz)
+                       --c_reg <= a_reg and b_reg;
+
+                       -- Minimum period: 4.603ns (Maximum Frequency: 217.273MHz)
+                       --c_reg <= std_logic_vector(unsigned(a_reg) + unsigned(b_reg));
+
+                       -- Minimum period: 5.641ns (Maximum Frequency: 177.289MHz)
+                       c_reg <= std_logic_vector(unsigned(a_reg) + unsigned(b_reg)) and x_reg;
+               end if;
+       end process;
+       c <= c_reg;
+
+end behavioral;