Rename ACK to RDY in merge pipeline control block

diff --git a/libraries/dsp/merge.vhd b/libraries/dsp/merge.vhd
index 9fc6dd0fec122c1d73de8e3f212f6d892decfabd..db51450f0deff1cfa261de4f8cb49e030afc9985 100644 (file)
--- a/libraries/dsp/merge.vhd
+++ b/libraries/dsp/merge.vhd
@@ -19,13 +19,13 @@ use unisim.vcomponents.all;
 entity merge is
        port (
                a_stb_i: in  std_logic;
-               a_ack_o: out std_logic;
+               a_rdy_o: out std_logic;
 
                b_stb_i: in  std_logic;
-               b_ack_o: out std_logic;
+               b_rdy_o: out std_logic;
 
                stb_o:   out std_logic;
-               ack_i:   in  std_logic
+               rdy_i:   in  std_logic
        );
 end merge;
 
@@ -38,7 +38,7 @@ begin
 
        costrobe <= a_stb_i and b_stb_i;
        stb_o    <= costrobe;
-       a_ack_o  <= costrobe and ack_i;
-       b_ack_o  <= costrobe and ack_i;
+       a_rdy_o  <= costrobe and rdy_i;
+       b_rdy_o  <= costrobe and rdy_i;
 
 end behavioral;