Remove builtin pipeline ctrl block from window sum

diff --git a/libraries/dsp/filter_windowsum.vhd b/libraries/dsp/filter_windowsum.vhd
index 901c9fcab09597beaa1a43d21e0226d5ac4177b6..443ff5ff86d9e4aac05a39109ada08c90c190e08 100644 (file)
--- a/libraries/dsp/filter_windowsum.vhd
+++ b/libraries/dsp/filter_windowsum.vhd
@@ -15,12 +15,9 @@ entity filter_windowsum is
                rst_i: in  std_logic;
                clk_i: in  std_logic;
 
-               stb_i: in  std_logic;
-               rdy_o: out std_logic;
-               dat_i: in  std_logic_vector(WIDTH-1 downto 0);
+               en_i:  in  std_logic;
 
-               stb_o: out std_logic;
-               rdy_i: in  std_logic;
+               dat_i: in  std_logic_vector(WIDTH-1 downto 0);
                dat_o: out std_logic_vector(WIDTH+integer(ceil(log2(real(WINDOW))))-1 downto 0)
        );
 end filter_windowsum;
@@ -30,34 +27,29 @@ architecture behavioral of filter_windowsum is
 
        constant ACC_WIDTH: positive := WIDTH+integer(ceil(log2(real(WINDOW))));
 
-       signal enable:      std_logic;
+       signal value_head: std_logic_vector(WIDTH-1 downto 0);
+       signal value_tail: std_logic_vector(WIDTH-1 downto 0);
 
-       signal value_head:  std_logic_vector(WIDTH-1 downto 0);
-       signal value_tail:  std_logic_vector(WIDTH-1 downto 0);
-
-       signal accumulator: std_logic_vector(ACC_WIDTH-1 downto 0);
-       signal value_sum:   signed(ACC_WIDTH-1 downto 0);
+       signal acc_reg:    signed(ACC_WIDTH-1 downto 0);
+       signal value_sum:  signed(ACC_WIDTH-1 downto 0);
 
 begin
 
        value_head <= dat_i;
-       value_sum <= signed(accumulator) + signed(value_head) - signed(value_tail);
+       value_sum <= signed(acc_reg) + signed(value_head) - signed(value_tail);
 
-       e_ctrl: entity work.pipectrl
-               generic map (WIDTH => ACC_WIDTH)
-               port map (
-                       rst_i => rst_i,
-                       clk_i => clk_i,
-                       en_o  => enable,
-                       stb_i => stb_i,
-                       rdy_o => rdy_o,
-                       dat_i => std_logic_vector(value_sum),
-                       stb_o => stb_o,
-                       rdy_i => rdy_i,
-                       dat_o => accumulator
-               );
+       process (rst_i, clk_i, acc_reg, value_sum)
+       begin
+               if rising_edge(clk_i) then
+                       if rst_i = '1' then
+                               acc_reg <= (others => '0');
+                       elsif en_i = '1' then
+                               acc_reg <= value_sum;
+                       end if;
+               end if;
+       end process;
 
-       dat_o <= accumulator;
+       dat_o <= std_logic_vector(acc_reg);
 
        e_delay: entity work.delay_srl
                generic map (
@@ -67,7 +59,7 @@ begin
                port map (
                        rst_i => rst_i,
                        clk_i => clk_i,
-                       en_i  => enable,
+                       en_i  => en_i,
                        dat_i => value_head,
                        dat_o => value_tail
                );