Sign extend and fix sat bypass in gain block

diff --git a/libraries/dsp/pcm16_2ch_gain.vhd b/libraries/dsp/pcm16_2ch_gain.vhd
index 2bdbac2a580ffff75a13467c4771a8581105e564..9938214a7f48083c7d45012bbfe2e02574160253 100644 (file)
--- a/libraries/dsp/pcm16_2ch_gain.vhd
+++ b/libraries/dsp/pcm16_2ch_gain.vhd
@@ -42,14 +42,12 @@ architecture behavioral of pcm16_2ch_gain is
 
 begin
 
-       samp_l <= "00" & dat_i(15 downto  0);
-       samp_r <= "00" & dat_i(31 downto 16);
+       samp_l <= dat_i(15) & dat_i(15) & dat_i(15 downto  0);
+       samp_r <= dat_i(31) & dat_i(31) & dat_i(31 downto 16);
 
        out_l <= std_logic_vector(signed(samp_l) * signed(gain_l));
        out_r <= std_logic_vector(signed(samp_r) * signed(gain_r));
 
-       result <= (out_r(24 downto 9)) & (out_l(24 downto 9));
-
        e_sat_l: entity work.saturate
                generic map (WIDTH_IN => 27, WIDTH_OUT => 16)
                port map (dat_i => out_l(35 downto 9), dat_o => result_l);
@@ -58,6 +56,8 @@ begin
                generic map (WIDTH_IN => 27, WIDTH_OUT => 16)
                port map (dat_i => out_r(35 downto 9), dat_o => result_r);
 
+       result <= result_r & result_l;
+
        e_interstage: entity dsp.pipectrl
                generic map (WIDTH => 32)
                port map (