]> git.the-white-hart.net Git - vhdl/commitdiff
Add more documentation for PS2 and RS232 ifaces
authorrs <>
Sat, 28 Jun 2025 05:01:44 +0000 (00:01 -0500)
committerrs <>
Sat, 28 Jun 2025 05:01:44 +0000 (00:01 -0500)
libraries/ps2/ps2_host.vhd
libraries/ps2/ps2_host_wb.vhd
libraries/rs232/rs232_rx.vhd
libraries/rs232/rs232_tx.vhd
libraries/rs232/rs232_uart.vhd

index 00ea8b1586581b83a311ed63705e0d00fd44a405..9177d75a1224e7c3b49c9527f41b93d16573cd5e 100644 (file)
@@ -1,4 +1,6 @@
 --------------------------------------------------------------------------------
+-- ps2_host - Host PS2 (keyboard/mouse) interface
+--------------------------------------------------------------------------------
 -- Notes:
 --
 -- The interface to the system is Wishbone-like - ACK and DAT signals are only
index dbd0eac03b605bea9b03924c17568ab371e6aae5..eb7a599d9b6662a0b0a08d3bfb500e456cdfda2f 100644 (file)
@@ -1,4 +1,6 @@
 --------------------------------------------------------------------------------
+-- ps2_host_wb - Wishbone interface to host PS2 (keyboard/mouse) interface
+--------------------------------------------------------------------------------
 -- TODO: https://eecs.umich.edu/courses/doing_dsp/handout/SRL16E.pdf
 --       Play with using shift-registers to make this more dense
 --
 --
 -- FIXME: Missing OER signal (probably framing and parity errors too)
 --------------------------------------------------------------------------------
+-- WISHBONE DATASHEET
+--
+-- Wishbone specification used: Rev B.3
+-- Interface type: device
+-- Port size: 8-bit
+-- Operand sizes: 8-bit
+-- Endianness: undefined (port size same as granularity)
+-- Data transfer sequence: undefined
+-- Clock constraints: none
+-- Signals:
+-- * rst_i
+-- * clk_i
+-- * cyc_i
+-- * stb_i
+-- * we_i
+-- * ack_o
+-- * adr_i (3-bit)
+-- * dat_i (8-bit)
+-- * dat_o (8-bit)
+--------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
index 50900520b8d4542aedd0ea9b49388e820a47a3eb..9b5a4b9e52a27f34292dc6b26058bb1b447a9c58 100644 (file)
@@ -1,3 +1,7 @@
+--------------------------------------------------------------------------------
+-- rs232_rx - receiver for RS232 serial interface
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
index 7aa872a0a089e4fc37b8d3b081a0c937767cd06f..760b0db79cd63deb37b9e079b5346f9aea7b5a26 100644 (file)
@@ -1,3 +1,7 @@
+--------------------------------------------------------------------------------
+-- rs232_tx - transmitter for RS232 serial interface
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
index ba6b3e9c36cc25553fc67d4d033524fea9b206b9..69ce1a3e7376697b6cbf36ae7d59496eab4552b0 100644 (file)
@@ -1,4 +1,6 @@
 --------------------------------------------------------------------------------
+-- rs232_uart - Wishbone UART for RS232 serial interface
+--------------------------------------------------------------------------------
 -- TODO: https://eecs.umich.edu/courses/doing_dsp/handout/SRL16E.pdf
 --       Play with using shift-registers to make this more dense
 --