Update hardware test for nexys2 memctrl

diff --git a/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd b/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
index 1abd80d3ec6fe1fd9e4349ab0b75ba02095d1b81..a8d824f8712616d10f9d0448b0c253cbeced005f 100644 (file)
--- a/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
+++ b/libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
@@ -82,7 +82,7 @@ architecture behavioral of test_nexys2_mem_wb8_0 is
 begin
 
        mem_adr <= "000000000000000000" & adr(5 downto 0);
-       e_mem: entity work.mem_wb8_0
+       e_mem: entity work.mem_wb8_0_opt
                port map (
                        rst_i       => rst,
                        clk_i       => clk,
@@ -96,7 +96,7 @@ begin
                        dat_i       => dat_mosi,
                        dat_o       => mem_miso,
 
-                       wait_cycles => temp(4 downto 0),
+                       --wait_cycles => temp(4 downto 0),
 
                        MemOE       => d_MemOE,
                        MemWR       => d_MemWR,