Allow interstage register of zero width

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index cde463429441d572e0068273c4e381db286622ce..39b55e42aa1fdc22a6b8ca325315f99e53457c46 100644 (file)
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -4,7 +4,7 @@ use ieee.std_logic_1164.all;
 
 entity pipectrl is
        generic (
-               WIDTH: positive := 16
+               WIDTH: natural := 16
        );
        port (
                rst_i: in  std_logic;
@@ -14,7 +14,7 @@ entity pipectrl is
 
                stb_i: in  std_logic;
                rdy_o: out std_logic;
-               dat_i: in  std_logic_vector(WIDTH-1 downto 0);
+               dat_i: in  std_logic_vector(WIDTH-1 downto 0) := (others => '0');
 
                stb_o: out std_logic;
                rdy_i: in  std_logic;