signal rst_i: std_logic;
signal clk_i: std_logic;
- signal src_stb: std_logic;
- signal src_rdy: std_logic;
+ signal en_i: std_logic;
signal src_dat: std_logic_vector(7 downto 0);
-
- signal sum_stb: std_logic;
- signal sum_rdy: std_logic;
- signal sum_dat: std_logic_vector(7+2 downto 0);
+ signal sum_dat: std_logic_vector(9 downto 0);
begin
p_test: process
begin
-- Initial values
- sum_rdy <= '1';
- --src_dat <= x"80";
+ en_i <= '1';
+ src_dat <= x"80";
--src_dat <= x"7f";
- src_dat <= x"ff";
+ --src_dat <= x"ff";
-- Reset
rst_i <= '1';
wait;
end process;
- e_src: entity work.src_counter
- generic map (WIDTH => 8)
- port map (
- rst_i => rst_i,
- clk_i => clk_i,
- stb_o => src_stb,
- rdy_i => src_rdy,
- dat_o => open--src_dat
- );
-
e_windsum: entity work.filter_windowsum
generic map (
WIDTH => 8,
port map (
rst_i => rst_i,
clk_i => clk_i,
- stb_i => src_stb,
- rdy_o => src_rdy,
+ en_i => en_i,
dat_i => src_dat,
- stb_o => sum_stb,
- rdy_i => sum_rdy,
dat_o => sum_dat
);