Remove old commented code

diff --git a/libraries/nexys2/eppex_wb.vhd b/libraries/nexys2/eppex_wb.vhd
index f8a5d9d3fab1ff4e49e7256b327b1f680350c9b7..ac790f27a879c656d0fa337c72e6d7a128a6ea11 100644 (file)
--- a/libraries/nexys2/eppex_wb.vhd
+++ b/libraries/nexys2/eppex_wb.vhd
@@ -88,7 +88,6 @@ architecture behavioral of eppex_wb is
 begin
 
        -- Interface output should be in tristate until data is available for EPP to read
-       --EppDB <= epp_data_out_reg when epp_data_out_en = '1' else (others => 'Z');
        EppDB_o <= epp_data_out_reg;
        EppDB_w <= epp_data_out_en;
 
@@ -97,8 +96,8 @@ begin
        stb_o <= stb_reg;
        we_o  <= we_reg;
 
-       -- Always present the latched EPP data bus and latched address to the wishbone bus
-       dat_o <= EppDB_i;  -- epp_data_in_reg;
+       -- Always present the EPP data bus and latched address to the wishbone bus
+       dat_o <= EppDB_i;
        adr_o <= addr_reg;
 
        -- State register