+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-library utility;
-
-library work;
-
-
-entity nexys2_stm is
- port (
- clk_50: in std_logic;
-
- DB: inout std_logic_vector(7 downto 0);
- DstmIFCLK: in std_logic;
- DstmSLCS: in std_logic;
- DstmFLAGA: in std_logic;
- DstmFLAGB: in std_logic;
- DstmADR: out std_logic_vector(1 downto 0);
- DstmSLRD: out std_logic;
- DstmSLWR: out std_logic;
- DstmSLOE: out std_logic;
- DstmPKTEND: out std_logic
- );
-end nexys2_stm;
-
-
-architecture behavioral of nexys2_stm is
-
- signal dl_stb: std_logic;
- signal dl_rdy: std_logic;
- signal dl_dat: std_logic_vector(7 downto 0);
-
- signal ul_stb: std_logic;
- signal ul_ack: std_logic;
- signal ul_dat: std_logic_vector(7 downto 0);
-
- signal int_stb: std_logic;
- signal int_ack: std_logic;
- signal int_dat: std_logic_vector(7 downto 0);
-
-begin
-
- e_stm_wb: entity work.stmex_wb
- port map (
- ifclk => DstmIFCLK,
- stmen => DstmSLCS,
- db => DB,
- flaga => DstmFLAGA,
- flagb => DstmFLAGB,
- fifoadr => DstmADR,
- slrd => DstmSLRD,
- slwr => DstmSLWR,
- sloe => DstmSLOE,
- pktend => DstmPKTEND,
-
- dl_stb_o => dl_stb,
- dl_rdy_i => dl_rdy,
- dl_dat_o => dl_dat,
- dl_end_o => open,
-
- ul_stb_i => ul_stb,
- ul_rdy_o => ul_ack,
- ul_dat_i => ul_dat,
- ul_end_i => '0'
- );
-
- e_dl_fifo: entity utility.fifo_xclk
- port map (
- head_clk_i => DstmIFCLK,
- head_stb_i => dl_stb,
- head_ack_o => dl_rdy,
- head_dat_i => dl_dat,
-
- tail_clk_i => clk_50,
- tail_stb_o => int_stb,
- tail_ack_i => int_ack,
- tail_dat_o => int_dat
- );
-
- e_ul_fifo: entity utility.fifo_xclk
- port map (
- head_clk_i => clk_50,
- head_stb_i => int_stb,
- head_ack_o => int_ack,
- head_dat_i => int_dat,
-
- tail_clk_i => DstmIFCLK,
- tail_stb_o => ul_stb,
- tail_ack_i => ul_ack,
- tail_dat_o => ul_dat
- );
-
-end behavioral;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library simulated;
-
-
-entity test_nexys2stm is
-end test_nexys2stm;
-
-
-architecture behavior of test_nexys2stm is
-
- signal db: std_logic_vector(7 downto 0);
- signal ifclk: std_logic;
- signal slcs: std_logic;
- signal flaga: std_logic;
- signal flagb: std_logic;
- signal fifoadr: std_logic_vector(1 downto 0);
- signal slrd: std_logic;
- signal slwr: std_logic;
- signal sloe: std_logic;
- signal pktend: std_logic;
-
- signal dl_data: std_logic_vector(7 downto 0);
- signal ul_count: integer;
-
- signal clk_50: std_logic;
-
-begin
-
- p_test: process
- begin
- DB <= (others => 'Z');
- wait for 50 ns;
- dl_data <= x"a0"; wait for 0 ns;
- dl_data <= x"a1"; wait for 0 ns;
- dl_data <= x"a2"; wait for 0 ns;
- dl_data <= x"a3"; wait for 0 ns;
- dl_data <= x"a4"; wait for 0 ns;
- dl_data <= x"a5"; wait for 0 ns;
- dl_data <= x"a6"; wait for 0 ns;
- dl_data <= x"a7"; wait for 0 ns;
- ul_count <= 8; wait for 0 ns;
-
- wait for 600 ns;
-
- dl_data <= x"b0"; wait for 0 ns;
- dl_data <= x"b1"; wait for 0 ns;
- dl_data <= x"b2"; wait for 0 ns;
- dl_data <= x"b3"; wait for 0 ns;
- dl_data <= x"b4"; wait for 0 ns;
- dl_data <= x"b5"; wait for 0 ns;
- dl_data <= x"b6"; wait for 0 ns;
- dl_data <= x"b7"; wait for 0 ns;
- ul_count <= 8; wait for 0 ns;
-
- --dl_data <= x"c0"; wait for 0 ns;
- --dl_data <= x"c1"; wait for 0 ns;
- --dl_data <= x"c2"; wait for 0 ns;
- --dl_data <= x"c3"; wait for 0 ns;
- --dl_data <= x"c4"; wait for 0 ns;
- --dl_data <= x"c5"; wait for 0 ns;
- --dl_data <= x"c6"; wait for 0 ns;
- --dl_data <= x"c7"; wait for 0 ns;
- --dl_data <= x"d0"; wait for 0 ns;
- --dl_data <= x"d1"; wait for 0 ns;
- --dl_data <= x"d2"; wait for 0 ns;
- --dl_data <= x"d3"; wait for 0 ns;
- --dl_data <= x"d4"; wait for 0 ns;
- --dl_data <= x"d5"; wait for 0 ns;
- --dl_data <= x"d6"; wait for 0 ns;
- --dl_data <= x"d7"; wait for 0 ns;
-
- wait;
- end process;
-
-
- e_host: entity simulated.stmhost
- port map (
- ifclk => ifclk,
- slcs => slcs,
- flaga => flaga,
- flagb => flagb,
- slrd => slrd,
- slwr => slwr,
- sloe => sloe,
- pktend => pktend,
- fifoadr => fifoadr,
- db => db,
-
- host_dl_data => dl_data,
- host_ul_count => ul_count
- );
-
-
- e_uut: entity work.nexys2_stm
- port map (
- clk_50 => clk_50,
- DB => db,
- DstmIFCLK => ifclk,
- DstmSLCS => slcs,
- DstmFLAGA => flaga,
- DstmFLAGB => flagb,
- DstmADR => fifoadr,
- DstmSLRD => slrd,
- DstmSLWR => slwr,
- DstmSLOE => sloe,
- DstmPKTEND => pktend
- );
-
- p_clk: process
- begin
- clk_50 <= '0';
- wait for 10 ns;
- clk_50 <= '1';
- wait for 10 ns;
- end process;
-
-end;
signal ifclk: std_logic;
signal stmen: std_logic;
signal db: std_logic_vector(7 downto 0);
+ signal db_o: std_logic_vector(7 downto 0);
signal flaga: std_logic;
signal flagb: std_logic;
signal fifoadr: std_logic_vector(1 downto 0);
wait;
end process;
- e_dl_fifo: entity utility.fifo_xclk
+ e_dl_fifo: entity utility.sync_fifo_2k_8
port map (
+ head_rst_i => '0',
head_clk_i => ifclk,
head_stb_i => dl_stb,
- head_ack_o => dl_rdy,
+ head_rdy_o => dl_rdy,
head_dat_i => dl_dat,
+ tail_rst_i => '0',
tail_clk_i => ifclk,
tail_stb_o => int_stb,
tail_ack_i => int_ack,
tail_dat_o => int_dat
);
- e_ul_fifo: entity utility.fifo_xclk
+ e_ul_fifo: entity utility.sync_fifo_2k_8
port map (
+ head_rst_i => '0',
head_clk_i => ifclk,
head_stb_i => int_stb,
- head_ack_o => int_ack,
+ head_rdy_o => int_ack,
head_dat_i => int_dat,
+ tail_rst_i => '0',
tail_clk_i => ifclk,
tail_stb_o => ul_stb,
tail_ack_i => ul_rdy,
port map (
ifclk => ifclk,
stmen => stmen,
- db => db,
+ db_i => db,
+ db_o => db_o,
flaga => flaga,
flagb => flagb,
fifoadr => fifoadr,
dl_end_o => open, -- dl_end,
ul_stb_i => ul_stb,
- ul_rdy_o => ul_rdy,
+ ul_ack_o => ul_rdy,
ul_dat_i => ul_dat,
ul_end_i => '0' -- ul_end
);
+ db <= db_o when sloe = '0' else (others => 'Z');
e_host: entity simulated.stmhost
port map (
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