Add enable output to pipe control logic

diff --git a/libraries/dsp/pipectrl.vhd b/libraries/dsp/pipectrl.vhd
index b07b22fa8dc407051ddbda6351164416c6099afd..cde463429441d572e0068273c4e381db286622ce 100644 (file)
--- a/libraries/dsp/pipectrl.vhd
+++ b/libraries/dsp/pipectrl.vhd
@@ -10,6 +10,8 @@ entity pipectrl is
                rst_i: in  std_logic;
                clk_i: in  std_logic;
 
+               en_o:  out std_logic;
+
                stb_i: in  std_logic;
                rdy_o: out std_logic;
                dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -33,6 +35,7 @@ begin
        -- * it is currently empty
        -- * if the downstream stage is accepting the current data
        enable <= (not stb_reg) or rdy_i;
+       en_o   <= enable and stb_i;
 
        stb_o <= stb_reg;
        rdy_o <= enable;

diff --git a/libraries/dsp/pipectrl_runout.vhd b/libraries/dsp/pipectrl_runout.vhd
index 097f847d74fb4b93def4b58c9ad27fd6a6466345..2e9b7fdcfc1f8aa4e7203d33d6620f7e85c037aa 100644 (file)
--- a/libraries/dsp/pipectrl_runout.vhd
+++ b/libraries/dsp/pipectrl_runout.vhd
@@ -10,6 +10,8 @@ entity pipectrl_runout is
                rst_i: in  std_logic;
                clk_i: in  std_logic;
 
+               en_o:  out std_logic;
+
                stb_i: in  std_logic;
                rdy_o: out std_logic;
                dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -44,6 +46,7 @@ begin
        dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
        en      <= rdy_reg;
+       en_o    <= en and stb_i;
        rob_en  <= rdy_reg and (not rdy_i);
        rob_clr <= rdy_i;
 

diff --git a/libraries/dsp/pipectrl_runout_srl.vhd b/libraries/dsp/pipectrl_runout_srl.vhd
index 2213c7db8546382ff98fdaa92897b1f4736b8c6d..301d2f087992b2d8385149b5cb5e4d8b1f8e4a1a 100644 (file)
--- a/libraries/dsp/pipectrl_runout_srl.vhd
+++ b/libraries/dsp/pipectrl_runout_srl.vhd
@@ -13,6 +13,8 @@ entity pipectrl_runout_srl is
                rst_i: in  std_logic;
                clk_i: in  std_logic;
 
+               en_o:  out std_logic;
+
                stb_i: in  std_logic;
                rdy_o: out std_logic;
                dat_i: in  std_logic_vector(WIDTH-1 downto 0);
@@ -47,6 +49,7 @@ begin
        --dat_o <= rob_dat_reg when rob_stb_reg = '1' else dat_reg;
 
        en      <= rdy_reg;
+       en_o    <= en and stb_i;
        rob_en  <= rdy_reg and (not rdy_i);
        rob_clr <= rdy_i;
 

diff --git a/libraries/dsp/pipectrl_split.vhd b/libraries/dsp/pipectrl_split.vhd
index c3a0dd48c520ba8808a879005321d08a3650cb19..89fbd91322114878fd88395ba418f4e5acea6c61 100644 (file)
--- a/libraries/dsp/pipectrl_split.vhd
+++ b/libraries/dsp/pipectrl_split.vhd
@@ -10,6 +10,8 @@ entity pipectrl_split is
                rst_i:   in  std_logic;
                clk_i:   in  std_logic;
 
+               en_o:    out std_logic;
+
                stb_i:   in  std_logic;
                rdy_o:   out std_logic;
                dat_i:   in  std_logic_vector(WIDTH-1 downto 0);
@@ -43,6 +45,7 @@ begin
        b_rdy <= (not b_stb_reg) or b_rdy_i;
        load  <= a_rdy and b_rdy;
        rdy_o <= load;
+       en_o  <= load and stb_i;
 
        -- Full registers
        process (rst_i, clk_i, load, a_rdy_i, b_rdy_i)