use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library dsp;
+
library work;
architecture behavioral of nexys2_usb is
- signal rst: std_logic;
+ signal rst: std_logic;
+
+ signal wb_cyc: std_logic;
+ signal wb_stb: std_logic;
+ signal wb_we: std_logic;
+ signal wb_ack: std_logic;
+ signal wb_adr: std_logic_vector(7 downto 0);
+ signal wb_miso: std_logic_vector(7 downto 0);
+ signal wb_mosi: std_logic_vector(7 downto 0);
+
+ signal dl_stb: std_logic;
+ signal dl_rdy: std_logic;
+ signal dl_dat: std_logic_vector(7 downto 0);
+
+ signal deser_stb: std_logic;
+ signal deser_rdy: std_logic;
+ signal deser_dat: std_logic_vector(31 downto 0);
+
+ signal split_a_stb: std_logic;
+ signal split_a_rdy: std_logic;
+ signal split_b_stb: std_logic;
+ signal split_b_rdy: std_logic;
+ signal split_dat: std_logic_vector(31 downto 0);
+
+ signal gain_stb: std_logic;
+ signal gain_rdy: std_logic;
+ signal gain_dat: std_logic_vector(31 downto 0);
- signal wb_cyc: std_logic;
- signal wb_stb: std_logic;
- signal wb_we: std_logic;
- signal wb_ack: std_logic;
- signal wb_adr: std_logic_vector(7 downto 0);
- signal wb_miso: std_logic_vector(7 downto 0);
- signal wb_mosi: std_logic_vector(7 downto 0);
+ signal pass1_stb: std_logic;
+ signal pass1_rdy: std_logic;
+ signal pass1_dat: std_logic_vector(31 downto 0);
- signal stm_stb: std_logic;
- signal stm_ack: std_logic;
- signal stm_dat: std_logic_vector(7 downto 0);
+ signal delay_stb: std_logic;
+ signal delay_rdy: std_logic;
+ signal delay_en: std_logic;
+ signal delay_dat: std_logic_vector(31 downto 0);
+
+ signal pass2_stb: std_logic;
+ signal pass2_rdy: std_logic;
+ signal pass2_dat: std_logic_vector(31 downto 0);
+
+ signal noise_stb: std_logic;
+ signal noise_rdy: std_logic;
+ signal noise_dat: std_logic_vector(31 downto 0);
+
+ signal ngain_stb: std_logic;
+ signal ngain_rdy: std_logic;
+ signal ngain_dat: std_logic_vector(31 downto 0);
+
+ signal sum_stb: std_logic;
+ signal sum_rdy: std_logic;
+ signal sum_dat: std_logic_vector(31 downto 0);
+
+ signal ser_stb: std_logic;
+ signal ser_rdy: std_logic;
+ signal ser_dat: std_logic_vector(7 downto 0);
begin
epp_dat_o => wb_mosi,
stm_clk_i => clk_50,
- stm_dl_stb_o => stm_stb,
- stm_dl_ack_i => stm_ack,
- stm_dl_dat_o => stm_dat,
- stm_ul_stb_i => stm_stb,
- stm_ul_ack_o => stm_ack,
- stm_ul_dat_i => stm_dat
+ stm_dl_stb_o => dl_stb,
+ stm_dl_ack_i => dl_rdy,
+ stm_dl_dat_o => dl_dat,
+ stm_ul_stb_i => ser_stb,
+ stm_ul_ack_o => ser_rdy,
+ stm_ul_dat_i => ser_dat
+ );
+
+ ----------------------------------------------------------------------------
+ -- Stream processing pipeline
+
+ e_deserialize: entity dsp.deserialize
+ generic map (WIDTH => 8, N => 4)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ stb_i => dl_stb,
+ rdy_o => dl_rdy,
+ dat_i => dl_dat,
+
+ stb_o => deser_stb,
+ rdy_i => deser_rdy,
+ dat_o => deser_dat
+ );
+
+ ----------
+
+ e_split: entity dsp.pipectrl_split
+ generic map (WIDTH => 32)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ stb_i => deser_stb,
+ rdy_o => deser_rdy,
+ dat_i => deser_dat,
+
+ a_stb_o => split_a_stb,
+ a_rdy_i => split_a_rdy,
+
+ b_stb_o => split_b_stb,
+ b_rdy_i => split_b_rdy,
+
+ dat_o => split_dat
+ );
+
+ ----------
+
+ e_gain: entity dsp.pcm16_2ch_gain
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ gain_l => "000000000"&"010000000",
+ gain_r => "000000000"&"010000000",
+
+ stb_i => split_a_stb,
+ rdy_o => split_a_rdy,
+ dat_i => split_dat,
+
+ stb_o => gain_stb,
+ rdy_i => gain_rdy,
+ dat_o => gain_dat
+ );
+
+ --
+
+ e_pass1: entity dsp.pipectrl
+ generic map (WIDTH => 32)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ stb_i => split_b_stb,
+ rdy_o => split_b_rdy,
+ dat_i => split_dat,
+
+ stb_o => pass1_stb,
+ rdy_i => pass1_rdy,
+ dat_o => pass1_dat
);
+ ----------
+
+ e_delay_ctrl: entity dsp.pipectrl
+ generic map (WIDTH => 0)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ en_o => delay_en,
+
+ stb_i => gain_stb,
+ rdy_o => gain_rdy,
+ dat_i => open,
+
+ stb_o => delay_stb,
+ rdy_i => '1', --delay_rdy,
+ dat_o => open
+ );
+
+ e_delay_l: entity dsp.delay_bram
+ generic map (DELAY => 1023)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ en_i => delay_en,
+
+ dat_i => gain_dat(15 downto 0),
+ dat_o => delay_dat(15 downto 0)
+ );
+
+ e_delay_r: entity dsp.delay_bram
+ generic map (DELAY => 1023)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ en_i => delay_en,
+
+ dat_i => gain_dat(31 downto 16),
+ dat_o => delay_dat(31 downto 16)
+ );
+
+ --
+
+ e_pass2: entity dsp.pipectrl
+ generic map (WIDTH => 32)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ stb_i => pass1_stb,
+ rdy_o => pass1_rdy,
+ dat_i => pass1_dat,
+
+ stb_o => pass2_stb,
+ rdy_i => pass2_rdy,
+ dat_o => pass2_dat
+ );
+
+ ----------
+
+ e_noise: entity dsp.src_noise
+ generic map (WIDTH => 32)
+ port map (
+ clk_i => clk_50,
+
+ stb_o => noise_stb,
+ rdy_i => noise_rdy,
+ dat_o => noise_dat
+ );
+
+ e_ngain: entity dsp.pcm16_2ch_gain
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ gain_l => "000000000"&"000011000",
+ gain_r => "000000000"&"000011000",
+
+ stb_i => noise_stb,
+ rdy_o => noise_rdy,
+ dat_i => noise_dat,
+
+ stb_o => ngain_stb,
+ rdy_i => ngain_rdy,
+ dat_o => ngain_dat
+ );
+
+ e_sum: entity dsp.pcm16_2ch_sum
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ a_stb_i => ngain_stb,--delay_stb,
+ a_rdy_o => ngain_rdy,--delay_rdy,
+ a_dat_i => ngain_dat,--delay_dat,
+
+ b_stb_i => pass2_stb,
+ b_rdy_o => pass2_rdy,
+ b_dat_i => pass2_dat,
+
+ stb_o => sum_stb,
+ rdy_i => sum_rdy,
+ dat_o => sum_dat
+ );
+
+ e_serialize: entity dsp.serialize
+ generic map (WIDTH => 8, N => 4)
+ port map (
+ rst_i => rst,
+ clk_i => clk_50,
+
+ stb_i => sum_stb,
+ rdy_o => sum_rdy,
+ dat_i => sum_dat,
+
+ stb_o => ser_stb,
+ rdy_i => ser_rdy,
+ dat_o => ser_dat
+ );
+
+ ----------------------------------------------------------------------------
+
e_regs: entity work.host_regs_opt
port map (
rst_i => rst,
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