entity saturate is
+ generic (
+ WIDTH_IN: positive := 18;
+ WIDTH_OUT: positive := 16
+ );
port (
- dat_i: in std_logic_vector;
- dat_o: out std_logic_vector
+ dat_i: in std_logic_vector(WIDTH_IN-1 downto 0);
+ dat_o: out std_logic_vector(WIDTH_OUT-1 downto 0)
);
end saturate;
architecture behavioral of saturate is
- constant WIDTH_IN: positive := dat_i'length;
- constant WIDTH_OUT: positive := dat_o'length;
-
- constant MAX: std_logic_vector(WIDTH_OUT-1 downto 0) := (WIDTH_OUT-1 => '0', others => '1');
- constant MIN: std_logic_vector(WIDTH_OUT-1 downto 0) := (WIDTH_OUT-1 => '1', others => '0');
-
signal upper: std_logic_vector(WIDTH_IN downto WIDTH_OUT);
signal is_negative: std_logic;
is_saturated <= '0' when and_reduce(upper) = '1' or
nor_reduce(upper) = '1' else '1';
- dat_o <= dat_i(WIDTH_OUT-1 downto 0) when is_saturated = '0' else
- MAX when is_negative = '0' else
- MIN;
+ dat_o(WIDTH_OUT-2 downto 0) <= dat_i(WIDTH_OUT-2 downto 0) when is_saturated = '0' else
+ (others => '1') when is_negative = '0' else
+ (others => '0');
+
+ dat_o(WIDTH_OUT-1) <= dat_i(WIDTH_OUT-1) when is_saturated = '0' else
+ '0' when is_negative = '0' else
+ '1';
end behavioral;