Fix type issues and typo in sum block

diff --git a/libraries/dsp/pcm16_2ch_sum.vhd b/libraries/dsp/pcm16_2ch_sum.vhd
index 9213801dc7e478b89472c1dac72e6583852a5552..369f26ac9d64597995e058bda327ad660304e2dd 100644 (file)
--- a/libraries/dsp/pcm16_2ch_sum.vhd
+++ b/libraries/dsp/pcm16_2ch_sum.vhd
@@ -11,7 +11,7 @@ entity pcm16_2ch_sum is
                clk_i:   in  std_logic;
 
                a_stb_i: in  std_logic;
-               a_rdy_i: out std_logic;
+               a_rdy_o: out std_logic;
                a_dat_i: in  std_logic_vector(31 downto 0);
 
                b_stb_i: in  std_logic;
@@ -48,21 +48,21 @@ architecture behavioral of pcm16_2ch_sum is
 
 begin
 
-       samp_a_l <= a_dat_i(15 downto  0);
-       samp_a_r <= a_dat_i(31 downto 16);
-       samp_b_l <= b_dat_i(15 downto  0);
-       samp_b_r <= b_dat_i(31 downto 16);
+       samp_a_l <= signed(a_dat_i(15 downto  0));
+       samp_a_r <= signed(a_dat_i(31 downto 16));
+       samp_b_l <= signed(b_dat_i(15 downto  0));
+       samp_b_r <= signed(b_dat_i(31 downto 16));
 
        result_l <= samp_a_l + samp_b_l;
        result_r <= samp_a_r + samp_b_r;
 
        e_sat_l: entity work.saturate
                generic map (WIDTH_IN => 17, WIDTH_OUT => 16)
-               port map (dat_i => result_l, dat_o => sat_l);
+               port map (dat_i => std_logic_vector(result_l), dat_o => sat_l);
 
        e_sat_r: entity work.saturate
                generic map (WIDTH_IN => 17, WIDTH_OUT => 16)
-               port map (dat_i => result_r, dat_o => sat_r);
+               port map (dat_i => std_logic_vector(result_r), dat_o => sat_r);
 
        result <= sat_r & sat_l;