Add sparse array to simulated RAM

diff --git a/libraries/simulated/dev_mt45w8mw16bgx.vhd b/libraries/simulated/dev_mt45w8mw16bgx.vhd
index c1e176a5c415fc610ea80116c634b2ab6dfb2cd0..48a866f16f9c9e3f95dd525d66adc493bee20416 100644 (file)
--- a/libraries/simulated/dev_mt45w8mw16bgx.vhd
+++ b/libraries/simulated/dev_mt45w8mw16bgx.vhd
@@ -3,9 +3,14 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
+use work.sim_utility.all;
 
 
 entity mt45w8mw16bgx is
+       generic (
+               FILENAME: string  := "";
+               BASEADDR: natural := 0
+       );
        port (
                a:     in    std_logic_vector(22 downto 0);
                dq:    inout std_logic_vector(15 downto 0);
@@ -80,7 +85,7 @@ architecture behavioral of mt45w8mw16bgx is
        type word_array is array(natural range <>) of std_logic_vector(15 downto 0);
 
        -- Data array read signals
-       signal array_reg:  word_array(15 downto 0) := (others => (others => '1'));
+       shared variable ram_array: sparse_t;
        signal array_word: std_logic_vector(15 downto 0);
        signal read_word:  std_logic_vector(15 downto 0);
        signal xmask_addr: std_logic;
@@ -111,8 +116,23 @@ begin
        ----------------------------------------------------------------------------
        -- Asynchronous array reads
 
+       process
+       begin
+               if FILENAME = "" then
+                       ram_array := sparse_create;
+               else
+                       ram_array := sparse_create;
+                       sparse_load(ram_array, FILENAME, BASEADDR);
+               end if;
+               wait;
+       end process;
+
        -- Look up value from memory array, delay to allow for hold time
-       array_word <= array_reg(to_integer(unsigned(a))) after T_HZ;  -- T_OHZ, T_BHZ
+       process (a)
+       begin
+               array_word <= sparse_get(ram_array, to_integer(unsigned(a(a'high downto 1) & '1'))) &
+                             sparse_get(ram_array, to_integer(unsigned(a(a'high downto 1) & '0'))) after T_HZ;  -- T_OHZ, T_BHZ
+       end process;
 
        -- Generate mask for periods of time with invalid data
        -- FIXME: this may break hold time
@@ -161,16 +181,16 @@ begin
 
        -- Latch data on rising edge of write signal
        process (internal_we_ub_n, internal_we_lb_n)
+               variable word_addr: integer;
        begin
-               -- Changing (or tristating) DQ at the same moment as the write rising-edge should
-               -- be allowed (T_DH, data hold time, = 0 ns), but this breaks in ISim 14.7, hence
-               -- the 1 ps delay.
+               word_addr := to_integer(unsigned(a(a'high downto 1) & '0'));
+
                if rising_edge(internal_we_ub_n) then
-                       array_reg(to_integer(unsigned(a)))(15 downto 8) <= dq(15 downto 8)'delayed(1 ps);
+                       sparse_set(ram_array, word_addr + 1, dq(15 downto 8));
                end if;
 
                if rising_edge(internal_we_lb_n) then
-                       array_reg(to_integer(unsigned(a)))( 7 downto 0) <= dq( 7 downto 0)'delayed(1 ps);
+                       sparse_set(ram_array, word_addr + 0, dq( 7 downto 0));
                end if;
        end process;