Switch full-system sim test to latest CPU0

diff --git a/projects/cpu_0/tests/test_nexys2.vhd b/projects/cpu_0/tests/test_nexys2.vhd
index d8010b2850255c5e0181219349d6048a51c9253f..396fde2e99ed75c3393df9e17948d2cbff03a567 100644 (file)
--- a/projects/cpu_0/tests/test_nexys2.vhd
+++ b/projects/cpu_0/tests/test_nexys2.vhd
@@ -82,6 +82,7 @@ begin
        flash_ce <= "00" & FlashCS;
        flash_adr <= MemAdr & '0';
        e_flash: entity simulated.js28f128j3d75
+               generic map (FILENAME => "/home/ryan/Dropbox/Projects/VHDL/projects/cpu_0/asm/int_test2.bin")
                port map (
                        a      => flash_adr,
                        d      => MemDB,
@@ -111,7 +112,7 @@ begin
                );
 
 
-       e_uut: entity work.nexys2
+       e_uut: entity work.nexys2_speed
                port map (
                        clk_50     => clk_50,
                        DB         => DB,