Move power-on-reset into host_ctrl

diff --git a/libraries/nexys2/host_ctrl.vhd b/libraries/nexys2/host_ctrl.vhd
index 954af7eeb0a618105621985b236cb87b0fef4b1b..f80e4af26b122e59e88be1463320a21de7286bf0 100644 (file)
--- a/libraries/nexys2/host_ctrl.vhd
+++ b/libraries/nexys2/host_ctrl.vhd
@@ -261,6 +261,10 @@ end host_ctrl;
 
 architecture behavioral of host_ctrl is
 
+       -- Internal reset from power-on-reset generator
+       -- Can be re-reset with rst_i, and is also sent to device
+       signal rst_int:         std_logic;
+
        -- Host Wishbone bus from EPP bridge
        signal h_cyc:           std_logic;
        signal h_stb:           std_logic;
@@ -305,6 +309,16 @@ architecture behavioral of host_ctrl is
 
 begin
 
+       -- Power-on-reset
+       e_por: entity utility.power_on_reset
+               port map (
+                       rst_i => rst_i,
+                       clk_i => clk_i,
+                       rst_o => rst_int
+               );
+
+       d_rst_o <= rst_int or ctrl(7);
+
        -- EPP to Wishbone bridge
        e_epp_wb: entity work.epp_wb
                port map (
@@ -314,7 +328,7 @@ begin
                        EppDB   => EppDB,
                        EppWait => EppWait,
 
-                       rst_i   => rst_i,
+                       rst_i   => rst_int,
                        clk_i   => clk_i,
                        adr_o   => h_adr,
                        dat_i   => h_dat_miso,
@@ -360,7 +374,7 @@ begin
        -- Wishbone slave for control registers
        e_host_regs: entity work.host_regs
                port map (
-                       rst_i   => rst_i,
+                       rst_i   => rst_int,
                        clk_i   => clk_i,
 
                        h_cyc_i => h_cyc_ctl,
@@ -388,15 +402,12 @@ begin
                        sw      => sw
                );
 
-       -- Auxiliary signals to device
-       d_rst_o  <= ctrl(7);
-
 
        -- Wishbone slave for out-of-band memory controller
        e_mem_oob: entity work.mem_wb_basic
                port map (
                        clk_i      => clk_i,
-                       rst_i      => rst_i,
+                       rst_i      => rst_int,
 
                        cyc_i      => h_cyc_oob,
                        stb_i      => h_stb,
@@ -427,7 +438,7 @@ begin
        -- Wishbone slave for debug reads
        e_debug: entity utility.wb_debug
                port map (
-                       rst_i   => rst_i,
+                       rst_i   => rst_int,
                        clk_i   => clk_i,
                        cyc_i   => h_cyc_deb,
                        stb_i   => h_stb,

diff --git a/projects/cpu_0/nexys2.vhd b/projects/cpu_0/nexys2.vhd
index 53ced7ebc683a03a38018a24e1f1305c482fc382..eb581be9d3d3eed26ab4680926076234fef2a2c6 100644 (file)
--- a/projects/cpu_0/nexys2.vhd
+++ b/projects/cpu_0/nexys2.vhd
@@ -66,8 +66,6 @@ end nexys2;
 architecture behavioral of nexys2 is
 
        -- Device Wishbone SYSCON
-       signal g_rst:             std_logic;  -- Global power-on-reset
-       signal h_rst:             std_logic;  -- Host controller reset
        signal d_rst:             std_logic;  -- Device reset (P.O.R. or host)
        signal d_clk:             std_logic;  -- Device clock, in case DCM used instead of clk_50 later
 
@@ -175,14 +173,6 @@ begin
 
        d_clk <= clk_50;
 
-       e_por: entity utility.power_on_reset
-               port map (
-                       rst_i => '0',
-                       clk_i => d_clk,
-                       rst_o => g_rst
-               );
-
-       d_rst <= g_rst or h_rst;
 
        -- Flash: 0x00000000-0x00ffffff
        -- Ram:   0x01000000-0x01ffffff
@@ -296,10 +286,10 @@ begin
        e_host: entity nexys2_lib.host_ctrl
                port map (
                        clk_i        => d_clk,
-                       rst_i        => g_rst,
+                       rst_i        => '0',
 
                        -- Signals to the internal device
-                       d_rst_o      => h_rst,
+                       d_rst_o      => d_rst,
                        d_flags_o    => host_flags,
                        debug_i      => (others => '0'),
                        debug_o      => open,