Add clock enable to seven-seg-mux

diff --git a/libraries/nexys2/host_regs.vhd b/libraries/nexys2/host_regs.vhd
index ab56e95b81a8dfc6fba12947c59b3241da5e888f..e47af8f85f9908f47d373e4cdacc666e1c98def2 100644 (file)
--- a/libraries/nexys2/host_regs.vhd
+++ b/libraries/nexys2/host_regs.vhd
@@ -159,6 +159,7 @@ begin
        e_seven_seg_mux: entity work.seven_seg_mux
                port map (
                        clk_in   => clk_div(15),
+                       clk_en   => '1',
 
                        seg_0_in => regs(4)(6 downto 0),
                        seg_1_in => regs(5)(6 downto 0),

diff --git a/libraries/nexys2/seven_seg_mux.vhd b/libraries/nexys2/seven_seg_mux.vhd
index c2d56cd1c0a8b19e3bbee8b8803ae94ecb530f98..8ecfe064f89f66410a3dff0bb8e64b9a412e0e41 100644 (file)
--- a/libraries/nexys2/seven_seg_mux.vhd
+++ b/libraries/nexys2/seven_seg_mux.vhd
@@ -10,6 +10,7 @@ use ieee.numeric_std.all;
 entity seven_seg_mux is
        port (
                clk_in:   in  std_logic;
+               clk_en:   in  std_logic;
 
                seg_0_in: in  std_logic_vector(6 downto 0);
                seg_1_in: in  std_logic_vector(6 downto 0);
@@ -32,7 +33,7 @@ begin
 
        process(clk_in)
        begin
-               if rising_edge(clk_in) then
+               if rising_edge(clk_in) and clk_en = '1' then
                        an_reg <= an_reg + 1;
                end if;
        end process;