Separate resets in synchronizing FIFO

diff --git a/libraries/nexys2/usb.vhd b/libraries/nexys2/usb.vhd
index 50cdc5f4a827f8a524e623cd8319e5d1b89fdbbf..8a0956b18181d8f66f60ec9f3ac8797cf7dc34af 100644 (file)
--- a/libraries/nexys2/usb.vhd
+++ b/libraries/nexys2/usb.vhd
@@ -273,13 +273,13 @@ begin
        e_dl_fifo: entity utility.fifo_xclk
                generic map (SYNC_STAGES => SYNC_STAGES)
                port map (
-                       rst_i      => rst_i,
-
+                       head_rst_i => ifclk_rst,
                        head_clk_i => dstm_ifclk,
                        head_stb_i => dl_stb,
                        head_rdy_o => dl_rdy,
                        head_dat_i => dl_dat,
 
+                       tail_rst_i => stm_rst,
                        tail_clk_i => stm_clk_i,
                        tail_stb_o => stm_dl_stb_o,
                        tail_ack_i => stm_dl_ack_i,
@@ -290,13 +290,13 @@ begin
        e_ul_fifo: entity utility.fifo_xclk
                generic map (SYNC_STAGES => SYNC_STAGES)
                port map (
-                       rst_i      => rst_i,
-
+                       head_rst_i => stm_rst,
                        head_clk_i => stm_clk_i,
                        head_stb_i => stm_ul_stb_i,
                        head_rdy_o => stm_ul_ack_o,
                        head_dat_i => stm_ul_dat_i,
 
+                       tail_rst_i => ifclk_rst,
                        tail_clk_i => dstm_ifclk,
                        tail_stb_o => ul_stb,
                        tail_ack_i => ul_ack,

diff --git a/libraries/utility/fifo_xclk.vhd b/libraries/utility/fifo_xclk.vhd
index 09691788e69ade9a24260b91d228ef71095c0be2..3254cd257fc46c6ee20531a487c2e013e1c3c212 100644 (file)
--- a/libraries/utility/fifo_xclk.vhd
+++ b/libraries/utility/fifo_xclk.vhd
@@ -1,3 +1,27 @@
+--------------------------------------------------------------------------------
+-- fifo_xclk - cross clock domain FIFO
+--
+-- Generics:
+-- SYNC_STAGES - number of shift register stages to use when synchronizing
+--
+-- Ports:
+-- head_rst_i  - synchronous reset in head clock domain
+-- head_clk_i  - clock domain for data insertion
+-- head_stb_i  - high to trigger insertion of a byte
+-- head_rdy_o  - high when head can accept bytes
+-- head_dat_i  - byte to insert into the head
+-- tail_rst_i  - synchronous reset in tail clock domain
+-- tail_clk_i  - clock domain for data removal
+-- tail_stb_o  - high when a byte is available for removal
+-- tail_ack_i  - high to trigger acknowledgement of current tail byte
+-- tail_dat_o  - current tail byte when tail_stb_o is asserted
+--
+-- The head and tail reset are only separate to prevent duplication of reset
+-- synchronization logic.  Both ends should always be reset together, although
+-- it is acceptable for one end to come out of reset before the other due to
+-- differences in clock rates.
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -11,13 +35,13 @@ library utility;
 entity fifo_xclk is
        generic (SYNC_STAGES: positive := 2);
        port (
-               rst_i:      in  std_logic;
-
+               head_rst_i: in  std_logic;
                head_clk_i: in  std_logic;
                head_stb_i: in  std_logic;
                head_rdy_o: out std_logic;
                head_dat_i: in  std_logic_vector(7 downto 0);
 
+               tail_rst_i: in  std_logic;
                tail_clk_i: in  std_logic;
                tail_stb_o: out std_logic;
                tail_ack_i: in  std_logic;
@@ -49,14 +73,6 @@ begin
 
        -- Head logic
 
-       e_head_reset: entity utility.sync_sig
-               generic map (SYNC_STAGES => SYNC_STAGES+1)
-               port map (
-                       rst_i => rst_i,
-                       clk_i => head_clk_i,
-                       sig_o => head_rst
-               );
-
        e_xclk_tail: entity utility.sync_vec
                generic map (SYNC_STAGES => SYNC_STAGES)
                port map (
@@ -75,7 +91,7 @@ begin
        e_head_adr: entity utility.gray_counter
                generic map (N => 11)
                port map (
-                       rst_i => head_rst,
+                       rst_i => head_rst_i,
                        clk_i => head_clk_i,
                        ena_i => head_step,
                        gray  => head_adr_reg,
@@ -85,14 +101,6 @@ begin
 
        -- Tail logic
 
-       e_tail_reset: entity utility.sync_sig
-               generic map (SYNC_STAGES => SYNC_STAGES+1)
-               port map (
-                       rst_i => rst_i,
-                       clk_i => tail_clk_i,
-                       sig_o => tail_rst
-               );
-
        e_xclk_head: entity utility.sync_vec
                generic map (SYNC_STAGES => SYNC_STAGES)
                port map (
@@ -112,7 +120,7 @@ begin
        e_tail_adr: entity utility.gray_counter
                generic map (N => 11)
                port map (
-                       rst_i => tail_rst,
+                       rst_i => tail_rst_i,
                        clk_i => tail_clk_i,
                        ena_i => tail_step,
                        gray  => tail_adr_reg,