Adjust VGA vert timing and change sync polarity

diff --git a/libraries/vga/vga_counter.vhd b/libraries/vga/vga_counter.vhd
index 8f3d40005cefc0bf98a64c38bdaa5de75a88bf0c..b7ae86888286173647dc4c9adb820bf9a87e1596 100644 (file)
--- a/libraries/vga/vga_counter.vhd
+++ b/libraries/vga/vga_counter.vhd
@@ -22,7 +22,7 @@ entity vga_counter is
                V_DISPLAY:     integer := 480;
                V_FRONT_PORCH: integer := 10;
                V_SYNC_WIDTH:  integer := 2;
-               V_BACK_PORCH:  integer := 29
+               V_BACK_PORCH:  integer := 33
        );
        port (
                clk_50:  in  std_logic;
@@ -114,9 +114,9 @@ begin
        begin
                if rising_edge(clk_50) then
                        if h_sync_start = '1' then
-                               h_sync_reg <= '1';
-                       elsif h_sync_end = '1' then
                                h_sync_reg <= '0';
+                       elsif h_sync_end = '1' then
+                               h_sync_reg <= '1';
                        end if;
                end if;
        end process;
@@ -160,9 +160,9 @@ begin
        begin
                if rising_edge(clk_50) then
                        if v_sync_start = '1' then
-                               v_sync_reg <= '1';
-                       elsif v_sync_end = '1' then
                                v_sync_reg <= '0';
+                       elsif v_sync_end = '1' then
+                               v_sync_reg <= '1';
                        end if;
                end if;
        end process;