Initial commit of bytecode interpreter skeleton

Lots of work to do here, just saving progress.

diff --git a/asm_2/build.sh b/asm_2/build.sh
new file mode 100755 (executable)
index 0000000..51602be
--- /dev/null
+++ b/asm_2/build.sh
@@ -0,0 +1,3 @@
+#!/usr/bin/env bash
+
+avra interp.asm

diff --git a/asm_2/bytecode.txt b/asm_2/bytecode.txt
new file mode 100644 (file)
index 0000000..b08b4b6
--- /dev/null
+++ b/asm_2/bytecode.txt
@@ -0,0 +1,114 @@
+Bytecode "registers" and calling convention
+
+v0 - Temporary / Return value
+v1 \
+v2 |
+v3 |
+v4 | Arguments / Non-saved
+v5 |
+v6 |
+v7 /
+v8 \
+v9 |
+va | Saved
+vb |
+vc /
+vd - SP
+ve - RA
+vf - Flags
+
+
+
+Instruction encoding:
+
+               v[x], v[y]
+0XY0   add
+0XY1   sub
+0XY2   and
+0XY3   or
+0XY4   xor
+0XY5   nor
+0XY6   mov
+0XY7   mul
+0XY8   div
+0XY9   cmp
+0XYA   test
+0XYB
+0XYC
+0XYD
+0XYE
+0XYF   jal
+
+               v[x], imm32
+1XY0   add
+1XY1   sub
+1XY2   and
+1XY3   or
+1XY4   xor
+1XY5   nor
+1XY6   mov
+1XY7   mul
+1XY8   div
+1XY9   cmp
+1XYA   test
+1XYB
+1XYC
+1XYD
+1XYE
+1XYF   jal
+
+               v[x], y
+2XY0   add
+2XY1   sub
+2XY2   shl
+2XY3   shrl
+2XY4   shra
+2XY5   rol
+2XY6   ror
+2XY7
+2XY8
+2XY9   spi
+2XYA   mft
+2XYB   mtt
+2XYC   din
+2XYD   dout
+2XYE   ain
+2XYF   aout
+
+               v[x], v[y]+n
+3XYn   ldb
+4XYn   ldh
+5XYn   ldw
+6XYn   stb
+7XYn   sth
+8XYn   stw
+
+9
+
+Annn   avr     zext(nnn)
+
+               pc+sext(nn)
+B0nn   bz
+B1nn   bnz
+B2nn   bgt
+B3nn   blt
+B4nn   blte
+B5nn   bgte
+B6nn   bc
+B7nn   bnc
+B8nn
+B9nn
+BAnn
+BBnn
+BCnn
+BDnn
+BEnn
+BFnn
+
+Cnnn   jal     pc+sext(nnn) (implicit VE as link register)
+
+Dnnn   jmp     pc+sext(nnn)
+
+E
+F
+

diff --git a/asm_2/clean.sh b/asm_2/clean.sh
new file mode 100755 (executable)
index 0000000..21be122
--- /dev/null
+++ b/asm_2/clean.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+rm -f *.hex
+rm -f *.cof
+rm -f *.obj

diff --git a/asm_2/interp.asm b/asm_2/interp.asm
new file mode 100644 (file)
index 0000000..cd808d3
--- /dev/null
+++ b/asm_2/interp.asm
@@ -0,0 +1,393 @@
+.include "./m328Pdef.inc"
+
+
+; ------------------------------------------------------------------------------
+; Registers
+
+; r0  ----- Temp (r0:r1 are MUL output, so can't use long-term)
+; r1  ----- Temp
+; r2  l\___ Interpreter program counter
+; r3  h/
+; r4  l\___ Current interpreted instruction
+; r5  h/
+; r6  l\
+; r7   |___ Operand A / instruction result
+; r8   |
+; r9  h/
+; r10 l\
+; r11  |___ Operand B / instruction result part 2 (mul/div)
+; r12  |
+; r13 h/
+; r14 ----- New flags register value (VF)
+; r15
+; r16 l\___ Pointer to V[X]
+; r17 h/
+; r18
+; r19
+; r20
+; r21
+; r22
+; r23
+; r24 ----- Temp
+; r25 ----- Temp
+; r26 l\_X  HARE reserved
+; r27 h/
+; r28 l\_Y
+; r29 h/
+; r30 l\_Z
+; r31 h/
+
+
+
+; ------------------------------------------------------------------------------
+; Interrupt vector table
+
+.cseg
+
+; FIXME: move everything to the bootloader section, let bytecode take low mem
+.org 0x0000
+       rjmp    reset     ; RESET
+       reti
+       reti              ; INT0
+       reti
+       reti              ; INT1
+       reti
+       reti              ; PCINT0
+       reti
+       reti              ; PCINT1
+       reti
+       reti              ; PCINT2
+       reti
+       reti              ; WDT
+       reti
+       reti              ; TIMER2 COMPA
+       reti
+       reti              ; TIMER2 COMPB
+       reti
+       reti              ; TIMER2 OVF
+       reti
+       reti              ; TIMER1 CAPT
+       reti
+       reti              ; TIMER1 COMPA
+       reti
+       reti              ; TIMER1 COMPB
+       reti
+       reti              ; TIMER1 OVF
+       reti
+       reti              ; TIMER0 COMPA
+       reti
+       reti              ; TIMER0 COMPB
+       reti
+       reti              ; TIMER0 OVF
+       reti
+       reti              ; SPI, STC
+       reti
+       reti              ; USART, RX
+       reti
+       reti              ; USART, UDRE
+       reti
+       reti              ; USART, TX
+       reti
+       reti              ; ADC
+       reti
+       reti              ; EE READY
+       reti
+       reti              ; ANALOG COMP
+       reti
+       reti              ; TWI
+       reti
+       reti              ; SPM READY
+       reti
+
+
+; ------------------------------------------------------------------------------
+; Reset entry point
+
+reset:
+       ; ----- Disable interrupts and set stack pointer to top of SRAM
+
+       eor     r25, r25
+       out     SREG, r25
+       ldi     r25, HIGH(RAMEND)
+       out     SPH, r25
+       ldi     r25, LOW(RAMEND)
+       out     SPL, r25
+
+       ; ----- Reset interpreter state
+
+       ; TODO
+
+       ; --------------------------------------------------------------
+       ; Main loop
+loop:
+       ; Check for pin change interrupt and debounce
+       ; TODO
+
+       ; Fetch instruction
+       movw    ZL, r2
+       lpm     r4, Z+
+       lpm     r5, Z+
+       movw    r2, ZL
+
+       ; Decode first operand, always register V[X]
+       mov     r16, r5
+       andi    r16, 0x0f
+       lsl     r16
+       lsl     r16
+       ldi     r17, 0x00
+       ldi     ZL, LOW(interp_regs)
+       ldi     ZH, HIGH(interp_regs)
+       movw    r16, ZL
+       ld      r6, Z+
+       ld      r7, Z+
+       ld      r8, Z+
+       ld      r9, Z+
+
+       ; Decode second operand based on instruction type
+       mov     r10, r5
+       asr     r10
+       asr     r10
+       asr     r10
+       asr     r10
+       eor     r0, r0
+       ldi     ZL, LOW(operand_jumptable)
+       ldi     ZH, HIGH(operand_jumptable)
+       add     ZL, r10
+       adc     ZH, r0
+       ijmp
+_decode_done:
+
+       ; Dispatch based on instruction type
+       ldi     ZL, LOW(f_dispatch_jumptable)
+       ldi     ZH, HIGH(f_dispatch_jumptable)
+       eor     r0, r0
+       add     ZL, r10
+       adc     ZH, r0
+_dispatch_done_writeback_flags:
+       ldi     ZL, LOW(interp_regs)
+       ldi     ZH, HIGH(interp_regs)
+       ldi     r25, 0x0e*4
+       add     ZL, r25
+       eor     r0, r0
+       adc     ZH, r0
+       st      Z, r14
+_dispatch_done_writeback_reg:
+       movw    ZL, r16
+       st      Z+, r6
+       st      Z+, r7
+       st      Z+, r8
+       st      Z+, r9
+_dispatch_done:
+
+       rjmp    loop
+
+
+; ------------------------------------------------------------------------------
+; Operand decoding
+
+operand_jumptable:
+       .dw     operand_VY
+       .dw     operand_imm32
+       .dw     operand_Y
+       .dw     operand_VY_N
+       .dw     operand_VY_N
+       .dw     operand_VY_N
+       .dw     operand_VY_N
+       .dw     operand_VY_N
+       .dw     operand_VY_N
+       .dw     operand_none
+       .dw     operand_0NNN
+       .dw     operand_PC_ssNN
+       .dw     operand_PC_sNNN
+       .dw     operand_PC_sNNN
+       .dw     operand_none
+       .dw     operand_none
+
+operand_VY:
+       rjmp    _decode_done
+
+operand_imm32:
+       rjmp    _decode_done
+
+operand_Y:
+       rjmp    _decode_done
+
+operand_VY_N:
+       rjmp    _decode_done
+
+operand_ssNN:
+       rjmp    _decode_done
+
+operand_0NNN:
+       rjmp    _decode_done
+
+operand_PC_ssNN:
+       rjmp    _decode_done
+
+operand_PC_sNNN:
+       rjmp    _decode_done
+
+operand_none:
+       rjmp    _decode_done
+
+
+; ------------------------------------------------------------------------------
+; Instruction dispatch
+
+f_dispatch_jumptable:
+       .dw     dispatch_alu
+       .dw     dispatch_alu
+       .dw     dispatch_imm4
+       .dw     exec_ldb
+       .dw     exec_ldh
+       .dw     exec_ldw
+       .dw     exec_stb
+       .dw     exec_sth
+       .dw     exec_stw
+       .dw     exec_nop
+       .dw     exec_avr
+       .dw     dispatch_branch
+       .dw     exec_jal_with_ve
+       .dw     exec_jmp
+       .dw     exec_nop
+       .dw     exec_nop
+
+alu_dispatch_jumptable:
+       .dw     exec_add
+       .dw     exec_sub
+       .dw     exec_and
+       .dw     exec_or
+       .dw     exec_xor
+       .dw     exec_nor
+       .dw     exec_mov
+       .dw     exec_mul
+       .dw     exec_div
+       .dw     exec_cmp
+       .dw     exec_test
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_jal
+
+imm4_dispatch_jumptable:
+       .dw     exec_add
+       .dw     exec_sub
+       .dw     exec_shl
+       .dw     exec_shrl
+       .dw     exec_shra
+       .dw     exec_rol
+       .dw     exec_ror
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_spi
+       .dw     exec_mft
+       .dw     exec_mtt
+       .dw     exec_din
+       .dw     exec_dout
+       .dw     exec_ain
+       .dw     exec_aout
+
+branch_dispatch_jumptable:
+       .dw     exec_bz
+       .dw     exec_bnz
+       .dw     exec_bgt
+       .dw     exec_blt
+       .dw     exec_blte
+       .dw     exec_bgte
+       .dw     exec_bc
+       .dw     exec_bnc
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+       .dw     exec_nop
+
+
+dispatch_alu:
+       ldi     ZL, LOW(alu_dispatch_jumptable)
+       ldi     ZH, HIGH(alu_dispatch_jumptable)
+       mov     r25, r4
+       andi    r25, 0x0f
+       eor     r1, r1
+       add     ZL, r0
+       adc     ZH, r1
+       ijmp
+
+dispatch_imm4:
+       ldi     ZL, LOW(imm4_dispatch_jumptable)
+       ldi     ZH, HIGH(imm4_dispatch_jumptable)
+       mov     r25, r4
+       andi    r25, 0x0f
+       eor     r1, r1
+       add     ZL, r0
+       adc     ZH, r1
+       ijmp
+
+dispatch_branch:
+       ldi     ZL, LOW(branch_dispatch_jumptable)
+       ldi     ZH, HIGH(branch_dispatch_jumptable)
+       mov     r25, r5
+       andi    r25, 0x0f
+       eor     r1, r1
+       add     ZL, r0
+       adc     ZH, r1
+       ijmp
+
+exec_nop:
+exec_add:
+exec_sub:
+exec_and:
+exec_or:
+exec_xor:
+exec_nor:
+exec_mov:
+exec_mul:
+exec_div:
+exec_cmp:
+exec_test:
+exec_jal:
+exec_shl:
+exec_shrl:
+exec_shra:
+exec_rol:
+exec_ror:
+exec_spi:
+exec_mft:
+exec_mtt:
+exec_din:
+exec_dout:
+exec_ain:
+exec_aout:
+exec_ldb:
+exec_ldh:
+exec_ldw:
+exec_stb:
+exec_sth:
+exec_stw:
+exec_avr:
+exec_bz:
+exec_bnz:
+exec_bgt:
+exec_blt:
+exec_blte:
+exec_bgte:
+exec_bc:
+exec_bnc:
+exec_jal_with_ve:
+exec_jmp:
+       rjmp    _dispatch_done
+
+
+; ------------------------------------------------------------------------------
+; Interpreter state
+
+.dseg
+
+; 16 general purpose 32-bit "registers" (V0-VF)
+interp_regs:
+       .byte   16*4
+

diff --git a/asm_2/m328Pdef.inc b/asm_2/m328Pdef.inc
new file mode 100644 (file)
index 0000000..1ff56b8
--- /dev/null
+++ b/asm_2/m328Pdef.inc
@@ -0,0 +1,977 @@
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************\r
+;***** Created: 2008-04-10 09:29 ******* Source: ATmega328P.xml **********\r
+;*************************************************************************\r
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y\r
+;* \r
+;* Number            : AVR000\r
+;* File Name         : "m328Pdef.inc"\r
+;* Title             : Register/Bit Definitions for the ATmega328P\r
+;* Date              : 2008-04-10\r
+;* Version           : 2.25\r
+;* Support E-mail    : avr@atmel.com\r
+;* Target MCU        : ATmega328P\r
+;* \r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and \r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;* \r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"\r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in    r16,PORTB             ;read PORTB latch\r
+;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out   PORTB,r16             ;output to PORTB\r
+;* \r
+;* in    r16,TIFR              ;read the Timer Interrupt Flag Register\r
+;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)\r
+;* rjmp  TOV0_is_set           ;jump if set\r
+;* ...                         ;otherwise do something else\r
+;*************************************************************************\r
+\r
+#ifndef _M328PDEF_INC_\r
+#define _M328PDEF_INC_\r
+\r
+\r
+#pragma partinc 0\r
+\r
+; ***** SPECIFY DEVICE ***************************************************\r
+.device ATmega328P\r
+;#pragma AVRPART ADMIN PART_NAME ATmega328P\r
+.equ   SIGNATURE_000   = 0x1e\r
+.equ   SIGNATURE_001   = 0x95\r
+.equ   SIGNATURE_002   = 0x0f\r
+\r
+;#pragma AVRPART CORE CORE_VERSION V2E\r
+\r
+\r
+; ***** I/O REGISTER DEFINITIONS *****************************************\r
+; NOTE:\r
+; Definitions marked "MEMORY MAPPED"are extended I/O ports\r
+; and cannot be used with IN/OUT instructions\r
+.equ   UDR0    = 0xc6  ; MEMORY MAPPED\r
+.equ   UBRR0L  = 0xc4  ; MEMORY MAPPED\r
+.equ   UBRR0H  = 0xc5  ; MEMORY MAPPED\r
+.equ   UCSR0C  = 0xc2  ; MEMORY MAPPED\r
+.equ   UCSR0B  = 0xc1  ; MEMORY MAPPED\r
+.equ   UCSR0A  = 0xc0  ; MEMORY MAPPED\r
+.equ   TWAMR   = 0xbd  ; MEMORY MAPPED\r
+.equ   TWCR    = 0xbc  ; MEMORY MAPPED\r
+.equ   TWDR    = 0xbb  ; MEMORY MAPPED\r
+.equ   TWAR    = 0xba  ; MEMORY MAPPED\r
+.equ   TWSR    = 0xb9  ; MEMORY MAPPED\r
+.equ   TWBR    = 0xb8  ; MEMORY MAPPED\r
+.equ   ASSR    = 0xb6  ; MEMORY MAPPED\r
+.equ   OCR2B   = 0xb4  ; MEMORY MAPPED\r
+.equ   OCR2A   = 0xb3  ; MEMORY MAPPED\r
+.equ   TCNT2   = 0xb2  ; MEMORY MAPPED\r
+.equ   TCCR2B  = 0xb1  ; MEMORY MAPPED\r
+.equ   TCCR2A  = 0xb0  ; MEMORY MAPPED\r
+.equ   OCR1BL  = 0x8a  ; MEMORY MAPPED\r
+.equ   OCR1BH  = 0x8b  ; MEMORY MAPPED\r
+.equ   OCR1AL  = 0x88  ; MEMORY MAPPED\r
+.equ   OCR1AH  = 0x89  ; MEMORY MAPPED\r
+.equ   ICR1L   = 0x86  ; MEMORY MAPPED\r
+.equ   ICR1H   = 0x87  ; MEMORY MAPPED\r
+.equ   TCNT1L  = 0x84  ; MEMORY MAPPED\r
+.equ   TCNT1H  = 0x85  ; MEMORY MAPPED\r
+.equ   TCCR1C  = 0x82  ; MEMORY MAPPED\r
+.equ   TCCR1B  = 0x81  ; MEMORY MAPPED\r
+.equ   TCCR1A  = 0x80  ; MEMORY MAPPED\r
+.equ   DIDR1   = 0x7f  ; MEMORY MAPPED\r
+.equ   DIDR0   = 0x7e  ; MEMORY MAPPED\r
+.equ   ADMUX   = 0x7c  ; MEMORY MAPPED\r
+.equ   ADCSRB  = 0x7b  ; MEMORY MAPPED\r
+.equ   ADCSRA  = 0x7a  ; MEMORY MAPPED\r
+.equ   ADCH    = 0x79  ; MEMORY MAPPED\r
+.equ   ADCL    = 0x78  ; MEMORY MAPPED\r
+.equ   TIMSK2  = 0x70  ; MEMORY MAPPED\r
+.equ   TIMSK1  = 0x6f  ; MEMORY MAPPED\r
+.equ   TIMSK0  = 0x6e  ; MEMORY MAPPED\r
+.equ   PCMSK1  = 0x6c  ; MEMORY MAPPED\r
+.equ   PCMSK2  = 0x6d  ; MEMORY MAPPED\r
+.equ   PCMSK0  = 0x6b  ; MEMORY MAPPED\r
+.equ   EICRA   = 0x69  ; MEMORY MAPPED\r
+.equ   PCICR   = 0x68  ; MEMORY MAPPED\r
+.equ   OSCCAL  = 0x66  ; MEMORY MAPPED\r
+.equ   PRR     = 0x64  ; MEMORY MAPPED\r
+.equ   CLKPR   = 0x61  ; MEMORY MAPPED\r
+.equ   WDTCSR  = 0x60  ; MEMORY MAPPED\r
+.equ   SREG    = 0x3f\r
+.equ   SPL     = 0x3d\r
+.equ   SPH     = 0x3e\r
+.equ   SPMCSR  = 0x37\r
+.equ   MCUCR   = 0x35\r
+.equ   MCUSR   = 0x34\r
+.equ   SMCR    = 0x33\r
+.equ   ACSR    = 0x30\r
+.equ   SPDR    = 0x2e\r
+.equ   SPSR    = 0x2d\r
+.equ   SPCR    = 0x2c\r
+.equ   GPIOR2  = 0x2b\r
+.equ   GPIOR1  = 0x2a\r
+.equ   OCR0B   = 0x28\r
+.equ   OCR0A   = 0x27\r
+.equ   TCNT0   = 0x26\r
+.equ   TCCR0B  = 0x25\r
+.equ   TCCR0A  = 0x24\r
+.equ   GTCCR   = 0x23\r
+.equ   EEARH   = 0x22\r
+.equ   EEARL   = 0x21\r
+.equ   EEDR    = 0x20\r
+.equ   EECR    = 0x1f\r
+.equ   GPIOR0  = 0x1e\r
+.equ   EIMSK   = 0x1d\r
+.equ   EIFR    = 0x1c\r
+.equ   PCIFR   = 0x1b\r
+.equ   TIFR2   = 0x17\r
+.equ   TIFR1   = 0x16\r
+.equ   TIFR0   = 0x15\r
+.equ   PORTD   = 0x0b\r
+.equ   DDRD    = 0x0a\r
+.equ   PIND    = 0x09\r
+.equ   PORTC   = 0x08\r
+.equ   DDRC    = 0x07\r
+.equ   PINC    = 0x06\r
+.equ   PORTB   = 0x05\r
+.equ   DDRB    = 0x04\r
+.equ   PINB    = 0x03\r
+\r
+\r
+; ***** BIT DEFINITIONS **************************************************\r
+\r
+; ***** USART0 ***********************\r
+; UDR0 - USART I/O Data Register\r
+.equ   UDR0_0  = 0     ; USART I/O Data Register bit 0\r
+.equ   UDR0_1  = 1     ; USART I/O Data Register bit 1\r
+.equ   UDR0_2  = 2     ; USART I/O Data Register bit 2\r
+.equ   UDR0_3  = 3     ; USART I/O Data Register bit 3\r
+.equ   UDR0_4  = 4     ; USART I/O Data Register bit 4\r
+.equ   UDR0_5  = 5     ; USART I/O Data Register bit 5\r
+.equ   UDR0_6  = 6     ; USART I/O Data Register bit 6\r
+.equ   UDR0_7  = 7     ; USART I/O Data Register bit 7\r
+\r
+; UCSR0A - USART Control and Status Register A\r
+.equ   MPCM0   = 0     ; Multi-processor Communication Mode\r
+.equ   U2X0    = 1     ; Double the USART transmission speed\r
+.equ   UPE0    = 2     ; Parity Error\r
+.equ   DOR0    = 3     ; Data overRun\r
+.equ   FE0     = 4     ; Framing Error\r
+.equ   UDRE0   = 5     ; USART Data Register Empty\r
+.equ   TXC0    = 6     ; USART Transmitt Complete\r
+.equ   RXC0    = 7     ; USART Receive Complete\r
+\r
+; UCSR0B - USART Control and Status Register B\r
+.equ   TXB80   = 0     ; Transmit Data Bit 8\r
+.equ   RXB80   = 1     ; Receive Data Bit 8\r
+.equ   UCSZ02  = 2     ; Character Size\r
+.equ   TXEN0   = 3     ; Transmitter Enable\r
+.equ   RXEN0   = 4     ; Receiver Enable\r
+.equ   UDRIE0  = 5     ; USART Data register Empty Interrupt Enable\r
+.equ   TXCIE0  = 6     ; TX Complete Interrupt Enable\r
+.equ   RXCIE0  = 7     ; RX Complete Interrupt Enable\r
+\r
+; UCSR0C - USART Control and Status Register C\r
+.equ   UCPOL0  = 0     ; Clock Polarity\r
+.equ   UCSZ00  = 1     ; Character Size\r
+.equ   UCPHA0  = UCSZ00        ; For compatibility\r
+.equ   UCSZ01  = 2     ; Character Size\r
+.equ   UDORD0  = UCSZ01        ; For compatibility\r
+.equ   USBS0   = 3     ; Stop Bit Select\r
+.equ   UPM00   = 4     ; Parity Mode Bit 0\r
+.equ   UPM01   = 5     ; Parity Mode Bit 1\r
+.equ   UMSEL00 = 6     ; USART Mode Select\r
+.equ   UMSEL0  = UMSEL00       ; For compatibility\r
+.equ   UMSEL01 = 7     ; USART Mode Select\r
+.equ   UMSEL1  = UMSEL01       ; For compatibility\r
+\r
+; UBRR0H - USART Baud Rate Register High Byte\r
+.equ   UBRR8   = 0     ; USART Baud Rate Register bit 8\r
+.equ   UBRR9   = 1     ; USART Baud Rate Register bit 9\r
+.equ   UBRR10  = 2     ; USART Baud Rate Register bit 10\r
+.equ   UBRR11  = 3     ; USART Baud Rate Register bit 11\r
+\r
+; UBRR0L - USART Baud Rate Register Low Byte\r
+.equ   UBRR0   = 0     ; USART Baud Rate Register bit 0\r
+.equ   UBRR1   = 1     ; USART Baud Rate Register bit 1\r
+.equ   UBRR2   = 2     ; USART Baud Rate Register bit 2\r
+.equ   UBRR3   = 3     ; USART Baud Rate Register bit 3\r
+.equ   UBRR4   = 4     ; USART Baud Rate Register bit 4\r
+.equ   UBRR5   = 5     ; USART Baud Rate Register bit 5\r
+.equ   UBRR6   = 6     ; USART Baud Rate Register bit 6\r
+.equ   UBRR7   = 7     ; USART Baud Rate Register bit 7\r
+\r
+\r
+; ***** TWI **************************\r
+; TWAMR - TWI (Slave) Address Mask Register\r
+.equ   TWAM0   = 1     ; \r
+.equ   TWAMR0  = TWAM0 ; For compatibility\r
+.equ   TWAM1   = 2     ; \r
+.equ   TWAMR1  = TWAM1 ; For compatibility\r
+.equ   TWAM2   = 3     ; \r
+.equ   TWAMR2  = TWAM2 ; For compatibility\r
+.equ   TWAM3   = 4     ; \r
+.equ   TWAMR3  = TWAM3 ; For compatibility\r
+.equ   TWAM4   = 5     ; \r
+.equ   TWAMR4  = TWAM4 ; For compatibility\r
+.equ   TWAM5   = 6     ; \r
+.equ   TWAMR5  = TWAM5 ; For compatibility\r
+.equ   TWAM6   = 7     ; \r
+.equ   TWAMR6  = TWAM6 ; For compatibility\r
+\r
+; TWBR - TWI Bit Rate register\r
+.equ   TWBR0   = 0     ; \r
+.equ   TWBR1   = 1     ; \r
+.equ   TWBR2   = 2     ; \r
+.equ   TWBR3   = 3     ; \r
+.equ   TWBR4   = 4     ; \r
+.equ   TWBR5   = 5     ; \r
+.equ   TWBR6   = 6     ; \r
+.equ   TWBR7   = 7     ; \r
+\r
+; TWCR - TWI Control Register\r
+.equ   TWIE    = 0     ; TWI Interrupt Enable\r
+.equ   TWEN    = 2     ; TWI Enable Bit\r
+.equ   TWWC    = 3     ; TWI Write Collition Flag\r
+.equ   TWSTO   = 4     ; TWI Stop Condition Bit\r
+.equ   TWSTA   = 5     ; TWI Start Condition Bit\r
+.equ   TWEA    = 6     ; TWI Enable Acknowledge Bit\r
+.equ   TWINT   = 7     ; TWI Interrupt Flag\r
+\r
+; TWSR - TWI Status Register\r
+.equ   TWPS0   = 0     ; TWI Prescaler\r
+.equ   TWPS1   = 1     ; TWI Prescaler\r
+.equ   TWS3    = 3     ; TWI Status\r
+.equ   TWS4    = 4     ; TWI Status\r
+.equ   TWS5    = 5     ; TWI Status\r
+.equ   TWS6    = 6     ; TWI Status\r
+.equ   TWS7    = 7     ; TWI Status\r
+\r
+; TWDR - TWI Data register\r
+.equ   TWD0    = 0     ; TWI Data Register Bit 0\r
+.equ   TWD1    = 1     ; TWI Data Register Bit 1\r
+.equ   TWD2    = 2     ; TWI Data Register Bit 2\r
+.equ   TWD3    = 3     ; TWI Data Register Bit 3\r
+.equ   TWD4    = 4     ; TWI Data Register Bit 4\r
+.equ   TWD5    = 5     ; TWI Data Register Bit 5\r
+.equ   TWD6    = 6     ; TWI Data Register Bit 6\r
+.equ   TWD7    = 7     ; TWI Data Register Bit 7\r
+\r
+; TWAR - TWI (Slave) Address register\r
+.equ   TWGCE   = 0     ; TWI General Call Recognition Enable Bit\r
+.equ   TWA0    = 1     ; TWI (Slave) Address register Bit 0\r
+.equ   TWA1    = 2     ; TWI (Slave) Address register Bit 1\r
+.equ   TWA2    = 3     ; TWI (Slave) Address register Bit 2\r
+.equ   TWA3    = 4     ; TWI (Slave) Address register Bit 3\r
+.equ   TWA4    = 5     ; TWI (Slave) Address register Bit 4\r
+.equ   TWA5    = 6     ; TWI (Slave) Address register Bit 5\r
+.equ   TWA6    = 7     ; TWI (Slave) Address register Bit 6\r
+\r
+\r
+; ***** TIMER_COUNTER_1 **************\r
+; TIMSK1 - Timer/Counter Interrupt Mask Register\r
+.equ   TOIE1   = 0     ; Timer/Counter1 Overflow Interrupt Enable\r
+.equ   OCIE1A  = 1     ; Timer/Counter1 Output CompareA Match Interrupt Enable\r
+.equ   OCIE1B  = 2     ; Timer/Counter1 Output CompareB Match Interrupt Enable\r
+.equ   ICIE1   = 5     ; Timer/Counter1 Input Capture Interrupt Enable\r
+\r
+; TIFR1 - Timer/Counter Interrupt Flag register\r
+.equ   TOV1    = 0     ; Timer/Counter1 Overflow Flag\r
+.equ   OCF1A   = 1     ; Output Compare Flag 1A\r
+.equ   OCF1B   = 2     ; Output Compare Flag 1B\r
+.equ   ICF1    = 5     ; Input Capture Flag 1\r
+\r
+; TCCR1A - Timer/Counter1 Control Register A\r
+.equ   WGM10   = 0     ; Waveform Generation Mode\r
+.equ   WGM11   = 1     ; Waveform Generation Mode\r
+.equ   COM1B0  = 4     ; Compare Output Mode 1B, bit 0\r
+.equ   COM1B1  = 5     ; Compare Output Mode 1B, bit 1\r
+.equ   COM1A0  = 6     ; Comparet Ouput Mode 1A, bit 0\r
+.equ   COM1A1  = 7     ; Compare Output Mode 1A, bit 1\r
+\r
+; TCCR1B - Timer/Counter1 Control Register B\r
+.equ   CS10    = 0     ; Prescaler source of Timer/Counter 1\r
+.equ   CS11    = 1     ; Prescaler source of Timer/Counter 1\r
+.equ   CS12    = 2     ; Prescaler source of Timer/Counter 1\r
+.equ   WGM12   = 3     ; Waveform Generation Mode\r
+.equ   WGM13   = 4     ; Waveform Generation Mode\r
+.equ   ICES1   = 6     ; Input Capture 1 Edge Select\r
+.equ   ICNC1   = 7     ; Input Capture 1 Noise Canceler\r
+\r
+; TCCR1C - Timer/Counter1 Control Register C\r
+.equ   FOC1B   = 6     ; \r
+.equ   FOC1A   = 7     ; \r
+\r
+; GTCCR - General Timer/Counter Control Register\r
+.equ   PSRSYNC = 0     ; Prescaler Reset Timer/Counter1 and Timer/Counter0\r
+.equ   TSM     = 7     ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** TIMER_COUNTER_2 **************\r
+; TIMSK2 - Timer/Counter Interrupt Mask register\r
+.equ   TOIE2   = 0     ; Timer/Counter2 Overflow Interrupt Enable\r
+.equ   TOIE2A  = TOIE2 ; For compatibility\r
+.equ   OCIE2A  = 1     ; Timer/Counter2 Output Compare Match A Interrupt Enable\r
+.equ   OCIE2B  = 2     ; Timer/Counter2 Output Compare Match B Interrupt Enable\r
+\r
+; TIFR2 - Timer/Counter Interrupt Flag Register\r
+.equ   TOV2    = 0     ; Timer/Counter2 Overflow Flag\r
+.equ   OCF2A   = 1     ; Output Compare Flag 2A\r
+.equ   OCF2B   = 2     ; Output Compare Flag 2B\r
+\r
+; TCCR2A - Timer/Counter2 Control Register A\r
+.equ   WGM20   = 0     ; Waveform Genration Mode\r
+.equ   WGM21   = 1     ; Waveform Genration Mode\r
+.equ   COM2B0  = 4     ; Compare Output Mode bit 0\r
+.equ   COM2B1  = 5     ; Compare Output Mode bit 1\r
+.equ   COM2A0  = 6     ; Compare Output Mode bit 1\r
+.equ   COM2A1  = 7     ; Compare Output Mode bit 1\r
+\r
+; TCCR2B - Timer/Counter2 Control Register B\r
+.equ   CS20    = 0     ; Clock Select bit 0\r
+.equ   CS21    = 1     ; Clock Select bit 1\r
+.equ   CS22    = 2     ; Clock Select bit 2\r
+.equ   WGM22   = 3     ; Waveform Generation Mode\r
+.equ   FOC2B   = 6     ; Force Output Compare B\r
+.equ   FOC2A   = 7     ; Force Output Compare A\r
+\r
+; TCNT2 - Timer/Counter2\r
+.equ   TCNT2_0 = 0     ; Timer/Counter 2 bit 0\r
+.equ   TCNT2_1 = 1     ; Timer/Counter 2 bit 1\r
+.equ   TCNT2_2 = 2     ; Timer/Counter 2 bit 2\r
+.equ   TCNT2_3 = 3     ; Timer/Counter 2 bit 3\r
+.equ   TCNT2_4 = 4     ; Timer/Counter 2 bit 4\r
+.equ   TCNT2_5 = 5     ; Timer/Counter 2 bit 5\r
+.equ   TCNT2_6 = 6     ; Timer/Counter 2 bit 6\r
+.equ   TCNT2_7 = 7     ; Timer/Counter 2 bit 7\r
+\r
+; OCR2A - Timer/Counter2 Output Compare Register A\r
+.equ   OCR2_0  = 0     ; Timer/Counter2 Output Compare Register Bit 0\r
+.equ   OCR2_1  = 1     ; Timer/Counter2 Output Compare Register Bit 1\r
+.equ   OCR2_2  = 2     ; Timer/Counter2 Output Compare Register Bit 2\r
+.equ   OCR2_3  = 3     ; Timer/Counter2 Output Compare Register Bit 3\r
+.equ   OCR2_4  = 4     ; Timer/Counter2 Output Compare Register Bit 4\r
+.equ   OCR2_5  = 5     ; Timer/Counter2 Output Compare Register Bit 5\r
+.equ   OCR2_6  = 6     ; Timer/Counter2 Output Compare Register Bit 6\r
+.equ   OCR2_7  = 7     ; Timer/Counter2 Output Compare Register Bit 7\r
+\r
+; OCR2B - Timer/Counter2 Output Compare Register B\r
+;.equ  OCR2_0  = 0     ; Timer/Counter2 Output Compare Register Bit 0\r
+;.equ  OCR2_1  = 1     ; Timer/Counter2 Output Compare Register Bit 1\r
+;.equ  OCR2_2  = 2     ; Timer/Counter2 Output Compare Register Bit 2\r
+;.equ  OCR2_3  = 3     ; Timer/Counter2 Output Compare Register Bit 3\r
+;.equ  OCR2_4  = 4     ; Timer/Counter2 Output Compare Register Bit 4\r
+;.equ  OCR2_5  = 5     ; Timer/Counter2 Output Compare Register Bit 5\r
+;.equ  OCR2_6  = 6     ; Timer/Counter2 Output Compare Register Bit 6\r
+;.equ  OCR2_7  = 7     ; Timer/Counter2 Output Compare Register Bit 7\r
+\r
+; ASSR - Asynchronous Status Register\r
+.equ   TCR2BUB = 0     ; Timer/Counter Control Register2 Update Busy\r
+.equ   TCR2AUB = 1     ; Timer/Counter Control Register2 Update Busy\r
+.equ   OCR2BUB = 2     ; Output Compare Register 2 Update Busy\r
+.equ   OCR2AUB = 3     ; Output Compare Register2 Update Busy\r
+.equ   TCN2UB  = 4     ; Timer/Counter2 Update Busy\r
+.equ   AS2     = 5     ; Asynchronous Timer/Counter2\r
+.equ   EXCLK   = 6     ; Enable External Clock Input\r
+\r
+; GTCCR - General Timer Counter Control register\r
+.equ   PSRASY  = 1     ; Prescaler Reset Timer/Counter2\r
+.equ   PSR2    = PSRASY        ; For compatibility\r
+;.equ  TSM     = 7     ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** AD_CONVERTER *****************\r
+; ADMUX - The ADC multiplexer Selection Register\r
+.equ   MUX0    = 0     ; Analog Channel and Gain Selection Bits\r
+.equ   MUX1    = 1     ; Analog Channel and Gain Selection Bits\r
+.equ   MUX2    = 2     ; Analog Channel and Gain Selection Bits\r
+.equ   MUX3    = 3     ; Analog Channel and Gain Selection Bits\r
+.equ   ADLAR   = 5     ; Left Adjust Result\r
+.equ   REFS0   = 6     ; Reference Selection Bit 0\r
+.equ   REFS1   = 7     ; Reference Selection Bit 1\r
+\r
+; ADCSRA - The ADC Control and Status register A\r
+.equ   ADPS0   = 0     ; ADC  Prescaler Select Bits\r
+.equ   ADPS1   = 1     ; ADC  Prescaler Select Bits\r
+.equ   ADPS2   = 2     ; ADC  Prescaler Select Bits\r
+.equ   ADIE    = 3     ; ADC Interrupt Enable\r
+.equ   ADIF    = 4     ; ADC Interrupt Flag\r
+.equ   ADATE   = 5     ; ADC  Auto Trigger Enable\r
+.equ   ADSC    = 6     ; ADC Start Conversion\r
+.equ   ADEN    = 7     ; ADC Enable\r
+\r
+; ADCSRB - The ADC Control and Status register B\r
+.equ   ADTS0   = 0     ; ADC Auto Trigger Source bit 0\r
+.equ   ADTS1   = 1     ; ADC Auto Trigger Source bit 1\r
+.equ   ADTS2   = 2     ; ADC Auto Trigger Source bit 2\r
+.equ   ACME    = 6     ; \r
+\r
+; ADCH - ADC Data Register High Byte\r
+.equ   ADCH0   = 0     ; ADC Data Register High Byte Bit 0\r
+.equ   ADCH1   = 1     ; ADC Data Register High Byte Bit 1\r
+.equ   ADCH2   = 2     ; ADC Data Register High Byte Bit 2\r
+.equ   ADCH3   = 3     ; ADC Data Register High Byte Bit 3\r
+.equ   ADCH4   = 4     ; ADC Data Register High Byte Bit 4\r
+.equ   ADCH5   = 5     ; ADC Data Register High Byte Bit 5\r
+.equ   ADCH6   = 6     ; ADC Data Register High Byte Bit 6\r
+.equ   ADCH7   = 7     ; ADC Data Register High Byte Bit 7\r
+\r
+; ADCL - ADC Data Register Low Byte\r
+.equ   ADCL0   = 0     ; ADC Data Register Low Byte Bit 0\r
+.equ   ADCL1   = 1     ; ADC Data Register Low Byte Bit 1\r
+.equ   ADCL2   = 2     ; ADC Data Register Low Byte Bit 2\r
+.equ   ADCL3   = 3     ; ADC Data Register Low Byte Bit 3\r
+.equ   ADCL4   = 4     ; ADC Data Register Low Byte Bit 4\r
+.equ   ADCL5   = 5     ; ADC Data Register Low Byte Bit 5\r
+.equ   ADCL6   = 6     ; ADC Data Register Low Byte Bit 6\r
+.equ   ADCL7   = 7     ; ADC Data Register Low Byte Bit 7\r
+\r
+; DIDR0 - Digital Input Disable Register\r
+.equ   ADC0D   = 0     ; \r
+.equ   ADC1D   = 1     ; \r
+.equ   ADC2D   = 2     ; \r
+.equ   ADC3D   = 3     ; \r
+.equ   ADC4D   = 4     ; \r
+.equ   ADC5D   = 5     ; \r
+\r
+\r
+; ***** ANALOG_COMPARATOR ************\r
+; ACSR - Analog Comparator Control And Status Register\r
+.equ   ACIS0   = 0     ; Analog Comparator Interrupt Mode Select bit 0\r
+.equ   ACIS1   = 1     ; Analog Comparator Interrupt Mode Select bit 1\r
+.equ   ACIC    = 2     ; Analog Comparator Input Capture Enable\r
+.equ   ACIE    = 3     ; Analog Comparator Interrupt Enable\r
+.equ   ACI     = 4     ; Analog Comparator Interrupt Flag\r
+.equ   ACO     = 5     ; Analog Compare Output\r
+.equ   ACBG    = 6     ; Analog Comparator Bandgap Select\r
+.equ   ACD     = 7     ; Analog Comparator Disable\r
+\r
+; DIDR1 - Digital Input Disable Register 1\r
+.equ   AIN0D   = 0     ; AIN0 Digital Input Disable\r
+.equ   AIN1D   = 1     ; AIN1 Digital Input Disable\r
+\r
+\r
+; ***** PORTB ************************\r
+; PORTB - Port B Data Register\r
+.equ   PORTB0  = 0     ; Port B Data Register bit 0\r
+.equ   PB0     = 0     ; For compatibility\r
+.equ   PORTB1  = 1     ; Port B Data Register bit 1\r
+.equ   PB1     = 1     ; For compatibility\r
+.equ   PORTB2  = 2     ; Port B Data Register bit 2\r
+.equ   PB2     = 2     ; For compatibility\r
+.equ   PORTB3  = 3     ; Port B Data Register bit 3\r
+.equ   PB3     = 3     ; For compatibility\r
+.equ   PORTB4  = 4     ; Port B Data Register bit 4\r
+.equ   PB4     = 4     ; For compatibility\r
+.equ   PORTB5  = 5     ; Port B Data Register bit 5\r
+.equ   PB5     = 5     ; For compatibility\r
+.equ   PORTB6  = 6     ; Port B Data Register bit 6\r
+.equ   PB6     = 6     ; For compatibility\r
+.equ   PORTB7  = 7     ; Port B Data Register bit 7\r
+.equ   PB7     = 7     ; For compatibility\r
+\r
+; DDRB - Port B Data Direction Register\r
+.equ   DDB0    = 0     ; Port B Data Direction Register bit 0\r
+.equ   DDB1    = 1     ; Port B Data Direction Register bit 1\r
+.equ   DDB2    = 2     ; Port B Data Direction Register bit 2\r
+.equ   DDB3    = 3     ; Port B Data Direction Register bit 3\r
+.equ   DDB4    = 4     ; Port B Data Direction Register bit 4\r
+.equ   DDB5    = 5     ; Port B Data Direction Register bit 5\r
+.equ   DDB6    = 6     ; Port B Data Direction Register bit 6\r
+.equ   DDB7    = 7     ; Port B Data Direction Register bit 7\r
+\r
+; PINB - Port B Input Pins\r
+.equ   PINB0   = 0     ; Port B Input Pins bit 0\r
+.equ   PINB1   = 1     ; Port B Input Pins bit 1\r
+.equ   PINB2   = 2     ; Port B Input Pins bit 2\r
+.equ   PINB3   = 3     ; Port B Input Pins bit 3\r
+.equ   PINB4   = 4     ; Port B Input Pins bit 4\r
+.equ   PINB5   = 5     ; Port B Input Pins bit 5\r
+.equ   PINB6   = 6     ; Port B Input Pins bit 6\r
+.equ   PINB7   = 7     ; Port B Input Pins bit 7\r
+\r
+\r
+; ***** PORTC ************************\r
+; PORTC - Port C Data Register\r
+.equ   PORTC0  = 0     ; Port C Data Register bit 0\r
+.equ   PC0     = 0     ; For compatibility\r
+.equ   PORTC1  = 1     ; Port C Data Register bit 1\r
+.equ   PC1     = 1     ; For compatibility\r
+.equ   PORTC2  = 2     ; Port C Data Register bit 2\r
+.equ   PC2     = 2     ; For compatibility\r
+.equ   PORTC3  = 3     ; Port C Data Register bit 3\r
+.equ   PC3     = 3     ; For compatibility\r
+.equ   PORTC4  = 4     ; Port C Data Register bit 4\r
+.equ   PC4     = 4     ; For compatibility\r
+.equ   PORTC5  = 5     ; Port C Data Register bit 5\r
+.equ   PC5     = 5     ; For compatibility\r
+.equ   PORTC6  = 6     ; Port C Data Register bit 6\r
+.equ   PC6     = 6     ; For compatibility\r
+\r
+; DDRC - Port C Data Direction Register\r
+.equ   DDC0    = 0     ; Port C Data Direction Register bit 0\r
+.equ   DDC1    = 1     ; Port C Data Direction Register bit 1\r
+.equ   DDC2    = 2     ; Port C Data Direction Register bit 2\r
+.equ   DDC3    = 3     ; Port C Data Direction Register bit 3\r
+.equ   DDC4    = 4     ; Port C Data Direction Register bit 4\r
+.equ   DDC5    = 5     ; Port C Data Direction Register bit 5\r
+.equ   DDC6    = 6     ; Port C Data Direction Register bit 6\r
+\r
+; PINC - Port C Input Pins\r
+.equ   PINC0   = 0     ; Port C Input Pins bit 0\r
+.equ   PINC1   = 1     ; Port C Input Pins bit 1\r
+.equ   PINC2   = 2     ; Port C Input Pins bit 2\r
+.equ   PINC3   = 3     ; Port C Input Pins bit 3\r
+.equ   PINC4   = 4     ; Port C Input Pins bit 4\r
+.equ   PINC5   = 5     ; Port C Input Pins bit 5\r
+.equ   PINC6   = 6     ; Port C Input Pins bit 6\r
+\r
+\r
+; ***** PORTD ************************\r
+; PORTD - Port D Data Register\r
+.equ   PORTD0  = 0     ; Port D Data Register bit 0\r
+.equ   PD0     = 0     ; For compatibility\r
+.equ   PORTD1  = 1     ; Port D Data Register bit 1\r
+.equ   PD1     = 1     ; For compatibility\r
+.equ   PORTD2  = 2     ; Port D Data Register bit 2\r
+.equ   PD2     = 2     ; For compatibility\r
+.equ   PORTD3  = 3     ; Port D Data Register bit 3\r
+.equ   PD3     = 3     ; For compatibility\r
+.equ   PORTD4  = 4     ; Port D Data Register bit 4\r
+.equ   PD4     = 4     ; For compatibility\r
+.equ   PORTD5  = 5     ; Port D Data Register bit 5\r
+.equ   PD5     = 5     ; For compatibility\r
+.equ   PORTD6  = 6     ; Port D Data Register bit 6\r
+.equ   PD6     = 6     ; For compatibility\r
+.equ   PORTD7  = 7     ; Port D Data Register bit 7\r
+.equ   PD7     = 7     ; For compatibility\r
+\r
+; DDRD - Port D Data Direction Register\r
+.equ   DDD0    = 0     ; Port D Data Direction Register bit 0\r
+.equ   DDD1    = 1     ; Port D Data Direction Register bit 1\r
+.equ   DDD2    = 2     ; Port D Data Direction Register bit 2\r
+.equ   DDD3    = 3     ; Port D Data Direction Register bit 3\r
+.equ   DDD4    = 4     ; Port D Data Direction Register bit 4\r
+.equ   DDD5    = 5     ; Port D Data Direction Register bit 5\r
+.equ   DDD6    = 6     ; Port D Data Direction Register bit 6\r
+.equ   DDD7    = 7     ; Port D Data Direction Register bit 7\r
+\r
+; PIND - Port D Input Pins\r
+.equ   PIND0   = 0     ; Port D Input Pins bit 0\r
+.equ   PIND1   = 1     ; Port D Input Pins bit 1\r
+.equ   PIND2   = 2     ; Port D Input Pins bit 2\r
+.equ   PIND3   = 3     ; Port D Input Pins bit 3\r
+.equ   PIND4   = 4     ; Port D Input Pins bit 4\r
+.equ   PIND5   = 5     ; Port D Input Pins bit 5\r
+.equ   PIND6   = 6     ; Port D Input Pins bit 6\r
+.equ   PIND7   = 7     ; Port D Input Pins bit 7\r
+\r
+\r
+; ***** TIMER_COUNTER_0 **************\r
+; TIMSK0 - Timer/Counter0 Interrupt Mask Register\r
+.equ   TOIE0   = 0     ; Timer/Counter0 Overflow Interrupt Enable\r
+.equ   OCIE0A  = 1     ; Timer/Counter0 Output Compare Match A Interrupt Enable\r
+.equ   OCIE0B  = 2     ; Timer/Counter0 Output Compare Match B Interrupt Enable\r
+\r
+; TIFR0 - Timer/Counter0 Interrupt Flag register\r
+.equ   TOV0    = 0     ; Timer/Counter0 Overflow Flag\r
+.equ   OCF0A   = 1     ; Timer/Counter0 Output Compare Flag 0A\r
+.equ   OCF0B   = 2     ; Timer/Counter0 Output Compare Flag 0B\r
+\r
+; TCCR0A - Timer/Counter  Control Register A\r
+.equ   WGM00   = 0     ; Waveform Generation Mode\r
+.equ   WGM01   = 1     ; Waveform Generation Mode\r
+.equ   COM0B0  = 4     ; Compare Output Mode, Fast PWm\r
+.equ   COM0B1  = 5     ; Compare Output Mode, Fast PWm\r
+.equ   COM0A0  = 6     ; Compare Output Mode, Phase Correct PWM Mode\r
+.equ   COM0A1  = 7     ; Compare Output Mode, Phase Correct PWM Mode\r
+\r
+; TCCR0B - Timer/Counter Control Register B\r
+.equ   CS00    = 0     ; Clock Select\r
+.equ   CS01    = 1     ; Clock Select\r
+.equ   CS02    = 2     ; Clock Select\r
+.equ   WGM02   = 3     ; \r
+.equ   FOC0B   = 6     ; Force Output Compare B\r
+.equ   FOC0A   = 7     ; Force Output Compare A\r
+\r
+; TCNT0 - Timer/Counter0\r
+.equ   TCNT0_0 = 0     ; \r
+.equ   TCNT0_1 = 1     ; \r
+.equ   TCNT0_2 = 2     ; \r
+.equ   TCNT0_3 = 3     ; \r
+.equ   TCNT0_4 = 4     ; \r
+.equ   TCNT0_5 = 5     ; \r
+.equ   TCNT0_6 = 6     ; \r
+.equ   TCNT0_7 = 7     ; \r
+\r
+; OCR0A - Timer/Counter0 Output Compare Register\r
+.equ   OCROA_0 = 0     ; \r
+.equ   OCROA_1 = 1     ; \r
+.equ   OCROA_2 = 2     ; \r
+.equ   OCROA_3 = 3     ; \r
+.equ   OCROA_4 = 4     ; \r
+.equ   OCROA_5 = 5     ; \r
+.equ   OCROA_6 = 6     ; \r
+.equ   OCROA_7 = 7     ; \r
+\r
+; OCR0B - Timer/Counter0 Output Compare Register\r
+.equ   OCR0B_0 = 0     ; \r
+.equ   OCR0B_1 = 1     ; \r
+.equ   OCR0B_2 = 2     ; \r
+.equ   OCR0B_3 = 3     ; \r
+.equ   OCR0B_4 = 4     ; \r
+.equ   OCR0B_5 = 5     ; \r
+.equ   OCR0B_6 = 6     ; \r
+.equ   OCR0B_7 = 7     ; \r
+\r
+; GTCCR - General Timer/Counter Control Register\r
+;.equ  PSRSYNC = 0     ; Prescaler Reset Timer/Counter1 and Timer/Counter0\r
+.equ   PSR10   = PSRSYNC       ; For compatibility\r
+;.equ  TSM     = 7     ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** EXTERNAL_INTERRUPT ***********\r
+; EICRA - External Interrupt Control Register\r
+.equ   ISC00   = 0     ; External Interrupt Sense Control 0 Bit 0\r
+.equ   ISC01   = 1     ; External Interrupt Sense Control 0 Bit 1\r
+.equ   ISC10   = 2     ; External Interrupt Sense Control 1 Bit 0\r
+.equ   ISC11   = 3     ; External Interrupt Sense Control 1 Bit 1\r
+\r
+; EIMSK - External Interrupt Mask Register\r
+.equ   INT0    = 0     ; External Interrupt Request 0 Enable\r
+.equ   INT1    = 1     ; External Interrupt Request 1 Enable\r
+\r
+; EIFR - External Interrupt Flag Register\r
+.equ   INTF0   = 0     ; External Interrupt Flag 0\r
+.equ   INTF1   = 1     ; External Interrupt Flag 1\r
+\r
+; PCICR - Pin Change Interrupt Control Register\r
+.equ   PCIE0   = 0     ; Pin Change Interrupt Enable 0\r
+.equ   PCIE1   = 1     ; Pin Change Interrupt Enable 1\r
+.equ   PCIE2   = 2     ; Pin Change Interrupt Enable 2\r
+\r
+; PCMSK2 - Pin Change Mask Register 2\r
+.equ   PCINT16 = 0     ; Pin Change Enable Mask 16\r
+.equ   PCINT17 = 1     ; Pin Change Enable Mask 17\r
+.equ   PCINT18 = 2     ; Pin Change Enable Mask 18\r
+.equ   PCINT19 = 3     ; Pin Change Enable Mask 19\r
+.equ   PCINT20 = 4     ; Pin Change Enable Mask 20\r
+.equ   PCINT21 = 5     ; Pin Change Enable Mask 21\r
+.equ   PCINT22 = 6     ; Pin Change Enable Mask 22\r
+.equ   PCINT23 = 7     ; Pin Change Enable Mask 23\r
+\r
+; PCMSK1 - Pin Change Mask Register 1\r
+.equ   PCINT8  = 0     ; Pin Change Enable Mask 8\r
+.equ   PCINT9  = 1     ; Pin Change Enable Mask 9\r
+.equ   PCINT10 = 2     ; Pin Change Enable Mask 10\r
+.equ   PCINT11 = 3     ; Pin Change Enable Mask 11\r
+.equ   PCINT12 = 4     ; Pin Change Enable Mask 12\r
+.equ   PCINT13 = 5     ; Pin Change Enable Mask 13\r
+.equ   PCINT14 = 6     ; Pin Change Enable Mask 14\r
+\r
+; PCMSK0 - Pin Change Mask Register 0\r
+.equ   PCINT0  = 0     ; Pin Change Enable Mask 0\r
+.equ   PCINT1  = 1     ; Pin Change Enable Mask 1\r
+.equ   PCINT2  = 2     ; Pin Change Enable Mask 2\r
+.equ   PCINT3  = 3     ; Pin Change Enable Mask 3\r
+.equ   PCINT4  = 4     ; Pin Change Enable Mask 4\r
+.equ   PCINT5  = 5     ; Pin Change Enable Mask 5\r
+.equ   PCINT6  = 6     ; Pin Change Enable Mask 6\r
+.equ   PCINT7  = 7     ; Pin Change Enable Mask 7\r
+\r
+; PCIFR - Pin Change Interrupt Flag Register\r
+.equ   PCIF0   = 0     ; Pin Change Interrupt Flag 0\r
+.equ   PCIF1   = 1     ; Pin Change Interrupt Flag 1\r
+.equ   PCIF2   = 2     ; Pin Change Interrupt Flag 2\r
+\r
+\r
+; ***** SPI **************************\r
+; SPDR - SPI Data Register\r
+.equ   SPDR0   = 0     ; SPI Data Register bit 0\r
+.equ   SPDR1   = 1     ; SPI Data Register bit 1\r
+.equ   SPDR2   = 2     ; SPI Data Register bit 2\r
+.equ   SPDR3   = 3     ; SPI Data Register bit 3\r
+.equ   SPDR4   = 4     ; SPI Data Register bit 4\r
+.equ   SPDR5   = 5     ; SPI Data Register bit 5\r
+.equ   SPDR6   = 6     ; SPI Data Register bit 6\r
+.equ   SPDR7   = 7     ; SPI Data Register bit 7\r
+\r
+; SPSR - SPI Status Register\r
+.equ   SPI2X   = 0     ; Double SPI Speed Bit\r
+.equ   WCOL    = 6     ; Write Collision Flag\r
+.equ   SPIF    = 7     ; SPI Interrupt Flag\r
+\r
+; SPCR - SPI Control Register\r
+.equ   SPR0    = 0     ; SPI Clock Rate Select 0\r
+.equ   SPR1    = 1     ; SPI Clock Rate Select 1\r
+.equ   CPHA    = 2     ; Clock Phase\r
+.equ   CPOL    = 3     ; Clock polarity\r
+.equ   MSTR    = 4     ; Master/Slave Select\r
+.equ   DORD    = 5     ; Data Order\r
+.equ   SPE     = 6     ; SPI Enable\r
+.equ   SPIE    = 7     ; SPI Interrupt Enable\r
+\r
+\r
+; ***** WATCHDOG *********************\r
+; WDTCSR - Watchdog Timer Control Register\r
+.equ   WDP0    = 0     ; Watch Dog Timer Prescaler bit 0\r
+.equ   WDP1    = 1     ; Watch Dog Timer Prescaler bit 1\r
+.equ   WDP2    = 2     ; Watch Dog Timer Prescaler bit 2\r
+.equ   WDE     = 3     ; Watch Dog Enable\r
+.equ   WDCE    = 4     ; Watchdog Change Enable\r
+.equ   WDP3    = 5     ; Watchdog Timer Prescaler Bit 3\r
+.equ   WDIE    = 6     ; Watchdog Timeout Interrupt Enable\r
+.equ   WDIF    = 7     ; Watchdog Timeout Interrupt Flag\r
+\r
+\r
+; ***** CPU **************************\r
+; SREG - Status Register\r
+.equ   SREG_C  = 0     ; Carry Flag\r
+.equ   SREG_Z  = 1     ; Zero Flag\r
+.equ   SREG_N  = 2     ; Negative Flag\r
+.equ   SREG_V  = 3     ; Two's Complement Overflow Flag\r
+.equ   SREG_S  = 4     ; Sign Bit\r
+.equ   SREG_H  = 5     ; Half Carry Flag\r
+.equ   SREG_T  = 6     ; Bit Copy Storage\r
+.equ   SREG_I  = 7     ; Global Interrupt Enable\r
+\r
+; OSCCAL - Oscillator Calibration Value\r
+.equ   CAL0    = 0     ; Oscillator Calibration Value Bit0\r
+.equ   CAL1    = 1     ; Oscillator Calibration Value Bit1\r
+.equ   CAL2    = 2     ; Oscillator Calibration Value Bit2\r
+.equ   CAL3    = 3     ; Oscillator Calibration Value Bit3\r
+.equ   CAL4    = 4     ; Oscillator Calibration Value Bit4\r
+.equ   CAL5    = 5     ; Oscillator Calibration Value Bit5\r
+.equ   CAL6    = 6     ; Oscillator Calibration Value Bit6\r
+.equ   CAL7    = 7     ; Oscillator Calibration Value Bit7\r
+\r
+; CLKPR - Clock Prescale Register\r
+.equ   CLKPS0  = 0     ; Clock Prescaler Select Bit 0\r
+.equ   CLKPS1  = 1     ; Clock Prescaler Select Bit 1\r
+.equ   CLKPS2  = 2     ; Clock Prescaler Select Bit 2\r
+.equ   CLKPS3  = 3     ; Clock Prescaler Select Bit 3\r
+.equ   CLKPCE  = 7     ; Clock Prescaler Change Enable\r
+\r
+; SPMCSR - Store Program Memory Control and Status Register\r
+.equ   SELFPRGEN       = 0     ; Self Programming Enable\r
+.equ   PGERS   = 1     ; Page Erase\r
+.equ   PGWRT   = 2     ; Page Write\r
+.equ   BLBSET  = 3     ; Boot Lock Bit Set\r
+.equ   RWWSRE  = 4     ; Read-While-Write section read enable\r
+.equ   RWWSB   = 6     ; Read-While-Write Section Busy\r
+.equ   SPMIE   = 7     ; SPM Interrupt Enable\r
+\r
+; MCUCR - MCU Control Register\r
+.equ   IVCE    = 0     ; \r
+.equ   IVSEL   = 1     ; \r
+.equ   PUD     = 4     ; \r
+.equ   BODSE   = 5     ; BOD Sleep Enable\r
+.equ   BODS    = 6     ; BOD Sleep\r
+\r
+; MCUSR - MCU Status Register\r
+.equ   PORF    = 0     ; Power-on reset flag\r
+.equ   EXTRF   = 1     ; External Reset Flag\r
+.equ   EXTREF  = EXTRF ; For compatibility\r
+.equ   BORF    = 2     ; Brown-out Reset Flag\r
+.equ   WDRF    = 3     ; Watchdog Reset Flag\r
+\r
+; SMCR - Sleep Mode Control Register\r
+.equ   SE      = 0     ; Sleep Enable\r
+.equ   SM0     = 1     ; Sleep Mode Select Bit 0\r
+.equ   SM1     = 2     ; Sleep Mode Select Bit 1\r
+.equ   SM2     = 3     ; Sleep Mode Select Bit 2\r
+\r
+; GPIOR2 - General Purpose I/O Register 2\r
+.equ   GPIOR20 = 0     ; \r
+.equ   GPIOR21 = 1     ; \r
+.equ   GPIOR22 = 2     ; \r
+.equ   GPIOR23 = 3     ; \r
+.equ   GPIOR24 = 4     ; \r
+.equ   GPIOR25 = 5     ; \r
+.equ   GPIOR26 = 6     ; \r
+.equ   GPIOR27 = 7     ; \r
+\r
+; GPIOR1 - General Purpose I/O Register 1\r
+.equ   GPIOR10 = 0     ; \r
+.equ   GPIOR11 = 1     ; \r
+.equ   GPIOR12 = 2     ; \r
+.equ   GPIOR13 = 3     ; \r
+.equ   GPIOR14 = 4     ; \r
+.equ   GPIOR15 = 5     ; \r
+.equ   GPIOR16 = 6     ; \r
+.equ   GPIOR17 = 7     ; \r
+\r
+; GPIOR0 - General Purpose I/O Register 0\r
+.equ   GPIOR00 = 0     ; \r
+.equ   GPIOR01 = 1     ; \r
+.equ   GPIOR02 = 2     ; \r
+.equ   GPIOR03 = 3     ; \r
+.equ   GPIOR04 = 4     ; \r
+.equ   GPIOR05 = 5     ; \r
+.equ   GPIOR06 = 6     ; \r
+.equ   GPIOR07 = 7     ; \r
+\r
+; PRR - Power Reduction Register\r
+.equ   PRADC   = 0     ; Power Reduction ADC\r
+.equ   PRUSART0        = 1     ; Power Reduction USART\r
+.equ   PRSPI   = 2     ; Power Reduction Serial Peripheral Interface\r
+.equ   PRTIM1  = 3     ; Power Reduction Timer/Counter1\r
+.equ   PRTIM0  = 5     ; Power Reduction Timer/Counter0\r
+.equ   PRTIM2  = 6     ; Power Reduction Timer/Counter2\r
+.equ   PRTWI   = 7     ; Power Reduction TWI\r
+\r
+\r
+; ***** EEPROM ***********************\r
+; EEARL - EEPROM Address Register Low Byte\r
+.equ   EEAR0   = 0     ; EEPROM Read/Write Access Bit 0\r
+.equ   EEAR1   = 1     ; EEPROM Read/Write Access Bit 1\r
+.equ   EEAR2   = 2     ; EEPROM Read/Write Access Bit 2\r
+.equ   EEAR3   = 3     ; EEPROM Read/Write Access Bit 3\r
+.equ   EEAR4   = 4     ; EEPROM Read/Write Access Bit 4\r
+.equ   EEAR5   = 5     ; EEPROM Read/Write Access Bit 5\r
+.equ   EEAR6   = 6     ; EEPROM Read/Write Access Bit 6\r
+.equ   EEAR7   = 7     ; EEPROM Read/Write Access Bit 7\r
+\r
+; EEARH - EEPROM Address Register High Byte\r
+.equ   EEAR8   = 0     ; EEPROM Read/Write Access Bit 8\r
+.equ   EEAR9   = 1     ; EEPROM Read/Write Access Bit 9\r
+\r
+; EEDR - EEPROM Data Register\r
+.equ   EEDR0   = 0     ; EEPROM Data Register bit 0\r
+.equ   EEDR1   = 1     ; EEPROM Data Register bit 1\r
+.equ   EEDR2   = 2     ; EEPROM Data Register bit 2\r
+.equ   EEDR3   = 3     ; EEPROM Data Register bit 3\r
+.equ   EEDR4   = 4     ; EEPROM Data Register bit 4\r
+.equ   EEDR5   = 5     ; EEPROM Data Register bit 5\r
+.equ   EEDR6   = 6     ; EEPROM Data Register bit 6\r
+.equ   EEDR7   = 7     ; EEPROM Data Register bit 7\r
+\r
+; EECR - EEPROM Control Register\r
+.equ   EERE    = 0     ; EEPROM Read Enable\r
+.equ   EEPE    = 1     ; EEPROM Write Enable\r
+.equ   EEMPE   = 2     ; EEPROM Master Write Enable\r
+.equ   EERIE   = 3     ; EEPROM Ready Interrupt Enable\r
+.equ   EEPM0   = 4     ; EEPROM Programming Mode Bit 0\r
+.equ   EEPM1   = 5     ; EEPROM Programming Mode Bit 1\r
+\r
+\r
+\r
+; ***** LOCKSBITS ********************************************************\r
+.equ   LB1     = 0     ; Lock bit\r
+.equ   LB2     = 1     ; Lock bit\r
+.equ   BLB01   = 2     ; Boot Lock bit\r
+.equ   BLB02   = 3     ; Boot Lock bit\r
+.equ   BLB11   = 4     ; Boot lock bit\r
+.equ   BLB12   = 5     ; Boot lock bit\r
+\r
+\r
+; ***** FUSES ************************************************************\r
+; LOW fuse bits\r
+.equ   CKSEL0  = 0     ; Select Clock Source\r
+.equ   CKSEL1  = 1     ; Select Clock Source\r
+.equ   CKSEL2  = 2     ; Select Clock Source\r
+.equ   CKSEL3  = 3     ; Select Clock Source\r
+.equ   SUT0    = 4     ; Select start-up time\r
+.equ   SUT1    = 5     ; Select start-up time\r
+.equ   CKOUT   = 6     ; Clock output\r
+.equ   CKDIV8  = 7     ; Divide clock by 8\r
+\r
+; HIGH fuse bits\r
+.equ   BOOTRST = 0     ; Select reset vector\r
+.equ   BOOTSZ0 = 1     ; Select boot size\r
+.equ   BOOTSZ1 = 2     ; Select boot size\r
+.equ   EESAVE  = 3     ; EEPROM memory is preserved through chip erase\r
+.equ   WDTON   = 4     ; Watchdog Timer Always On\r
+.equ   SPIEN   = 5     ; Enable Serial programming and Data Downloading\r
+.equ   DWEN    = 6     ; debugWIRE Enable\r
+.equ   RSTDISBL        = 7     ; External reset disable\r
+\r
+; EXTENDED fuse bits\r
+.equ   BODLEVEL0       = 0     ; Brown-out Detector trigger level\r
+.equ   BODLEVEL1       = 1     ; Brown-out Detector trigger level\r
+.equ   BODLEVEL2       = 2     ; Brown-out Detector trigger level\r
+\r
+\r
+\r
+; ***** CPU REGISTER DEFINITIONS *****************************************\r
+.def   XH      = r27\r
+.def   XL      = r26\r
+.def   YH      = r29\r
+.def   YL      = r28\r
+.def   ZH      = r31\r
+.def   ZL      = r30\r
+\r
+\r
+\r
+; ***** DATA MEMORY DECLARATIONS *****************************************\r
+.equ   FLASHEND        = 0x3fff        ; Note: Word address\r
+.equ   IOEND   = 0x00ff\r
+.equ   SRAM_START      = 0x0100\r
+.equ   SRAM_SIZE       = 2048\r
+.equ   RAMEND  = 0x08ff\r
+.equ   XRAMEND = 0x0000\r
+.equ   E2END   = 0x03ff\r
+.equ   EEPROMEND       = 0x03ff\r
+.equ   EEADRBITS       = 10\r
+;#pragma AVRPART MEMORY PROG_FLASH 32768\r
+;#pragma AVRPART MEMORY EEPROM 1024\r
+;#pragma AVRPART MEMORY INT_SRAM SIZE 2048\r
+;#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100\r
+\r
+\r
+\r
+; ***** BOOTLOADER DECLARATIONS ******************************************\r
+.equ   NRWW_START_ADDR = 0x3800\r
+.equ   NRWW_STOP_ADDR  = 0x3fff\r
+.equ   RWW_START_ADDR  = 0x0\r
+.equ   RWW_STOP_ADDR   = 0x37ff\r
+.equ   PAGESIZE        = 64\r
+.equ   FIRSTBOOTSTART  = 0x3f00\r
+.equ   SECONDBOOTSTART = 0x3e00\r
+.equ   THIRDBOOTSTART  = 0x3c00\r
+.equ   FOURTHBOOTSTART = 0x3800\r
+.equ   SMALLBOOTSTART  = FIRSTBOOTSTART\r
+.equ   LARGEBOOTSTART  = FOURTHBOOTSTART\r
+\r
+\r
+\r
+; ***** INTERRUPT VECTORS ************************************************\r
+.equ   INT0addr        = 0x0002        ; External Interrupt Request 0\r
+.equ   INT1addr        = 0x0004        ; External Interrupt Request 1\r
+.equ   PCI0addr        = 0x0006        ; Pin Change Interrupt Request 0\r
+.equ   PCI1addr        = 0x0008        ; Pin Change Interrupt Request 0\r
+.equ   PCI2addr        = 0x000a        ; Pin Change Interrupt Request 1\r
+.equ   WDTaddr = 0x000c        ; Watchdog Time-out Interrupt\r
+.equ   OC2Aaddr        = 0x000e        ; Timer/Counter2 Compare Match A\r
+.equ   OC2Baddr        = 0x0010        ; Timer/Counter2 Compare Match A\r
+.equ   OVF2addr        = 0x0012        ; Timer/Counter2 Overflow\r
+.equ   ICP1addr        = 0x0014        ; Timer/Counter1 Capture Event\r
+.equ   OC1Aaddr        = 0x0016        ; Timer/Counter1 Compare Match A\r
+.equ   OC1Baddr        = 0x0018        ; Timer/Counter1 Compare Match B\r
+.equ   OVF1addr        = 0x001a        ; Timer/Counter1 Overflow\r
+.equ   OC0Aaddr        = 0x001c        ; TimerCounter0 Compare Match A\r
+.equ   OC0Baddr        = 0x001e        ; TimerCounter0 Compare Match B\r
+.equ   OVF0addr        = 0x0020        ; Timer/Couner0 Overflow\r
+.equ   SPIaddr = 0x0022        ; SPI Serial Transfer Complete\r
+.equ   URXCaddr        = 0x0024        ; USART Rx Complete\r
+.equ   UDREaddr        = 0x0026        ; USART, Data Register Empty\r
+.equ   UTXCaddr        = 0x0028        ; USART Tx Complete\r
+.equ   ADCCaddr        = 0x002a        ; ADC Conversion Complete\r
+.equ   ERDYaddr        = 0x002c        ; EEPROM Ready\r
+.equ   ACIaddr = 0x002e        ; Analog Comparator\r
+.equ   TWIaddr = 0x0030        ; Two-wire Serial Interface\r
+.equ   SPMRaddr        = 0x0032        ; Store Program Memory Read\r
+\r
+.equ   INT_VECTORS_SIZE        = 52    ; size in words\r
+\r
+#endif  /* _M328PDEF_INC_ */\r
+\r
+; ***** END OF FILE ******************************************************\r

diff --git a/asm_2/program.sh b/asm_2/program.sh
new file mode 100755 (executable)
index 0000000..471116d
--- /dev/null
+++ b/asm_2/program.sh
@@ -0,0 +1,9 @@
+#!/usr/bin/env bash
+set -ve
+
+TARGET="atmega328p"
+PORT="/dev/ttyUSB0"
+PROGRAMMER="-P ${PORT} -b 19200 -c avrisp"
+
+avrdude ${PROGRAMMER} -p ${TARGET} -U flash:w:siggen.hex
+