Add default output reg value to jtag for sims

diff --git a/libraries/utility/jtag_reg.vhd b/libraries/utility/jtag_reg.vhd
index 69e3da47414484379dd2b6b6dccc444a8667f71d..0b4814af8f14af3b74689b580bea1aa16a98ae4f 100644 (file)
--- a/libraries/utility/jtag_reg.vhd
+++ b/libraries/utility/jtag_reg.vhd
@@ -30,7 +30,7 @@ architecture behavioral of jtag_reg is
        signal update_cross_reg: std_logic_vector(3 downto 0);
 
        signal shift_reg:  std_logic_vector(N-1 downto 0);
-       signal outbuf_reg: std_logic_vector(N-1 downto 0);
+       signal outbuf_reg: std_logic_vector(N-1 downto 0) := (others => '0');
 
 begin