--- /dev/null
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************\r
+;***** Created: 2008-04-10 09:29 ******* Source: ATmega328P.xml **********\r
+;*************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m328Pdef.inc"\r
+;* Title : Register/Bit Definitions for the ATmega328P\r
+;* Date : 2008-04-10\r
+;* Version : 2.25\r
+;* Support E-mail : avr@atmel.com\r
+;* Target MCU : ATmega328P\r
+;* \r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and \r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;* \r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"\r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;* \r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;*************************************************************************\r
+\r
+#ifndef _M328PDEF_INC_\r
+#define _M328PDEF_INC_\r
+\r
+\r
+#pragma partinc 0\r
+\r
+; ***** SPECIFY DEVICE ***************************************************\r
+.device ATmega328P\r
+;#pragma AVRPART ADMIN PART_NAME ATmega328P\r
+.equ SIGNATURE_000 = 0x1e\r
+.equ SIGNATURE_001 = 0x95\r
+.equ SIGNATURE_002 = 0x0f\r
+\r
+;#pragma AVRPART CORE CORE_VERSION V2E\r
+\r
+\r
+; ***** I/O REGISTER DEFINITIONS *****************************************\r
+; NOTE:\r
+; Definitions marked "MEMORY MAPPED"are extended I/O ports\r
+; and cannot be used with IN/OUT instructions\r
+.equ UDR0 = 0xc6 ; MEMORY MAPPED\r
+.equ UBRR0L = 0xc4 ; MEMORY MAPPED\r
+.equ UBRR0H = 0xc5 ; MEMORY MAPPED\r
+.equ UCSR0C = 0xc2 ; MEMORY MAPPED\r
+.equ UCSR0B = 0xc1 ; MEMORY MAPPED\r
+.equ UCSR0A = 0xc0 ; MEMORY MAPPED\r
+.equ TWAMR = 0xbd ; MEMORY MAPPED\r
+.equ TWCR = 0xbc ; MEMORY MAPPED\r
+.equ TWDR = 0xbb ; MEMORY MAPPED\r
+.equ TWAR = 0xba ; MEMORY MAPPED\r
+.equ TWSR = 0xb9 ; MEMORY MAPPED\r
+.equ TWBR = 0xb8 ; MEMORY MAPPED\r
+.equ ASSR = 0xb6 ; MEMORY MAPPED\r
+.equ OCR2B = 0xb4 ; MEMORY MAPPED\r
+.equ OCR2A = 0xb3 ; MEMORY MAPPED\r
+.equ TCNT2 = 0xb2 ; MEMORY MAPPED\r
+.equ TCCR2B = 0xb1 ; MEMORY MAPPED\r
+.equ TCCR2A = 0xb0 ; MEMORY MAPPED\r
+.equ OCR1BL = 0x8a ; MEMORY MAPPED\r
+.equ OCR1BH = 0x8b ; MEMORY MAPPED\r
+.equ OCR1AL = 0x88 ; MEMORY MAPPED\r
+.equ OCR1AH = 0x89 ; MEMORY MAPPED\r
+.equ ICR1L = 0x86 ; MEMORY MAPPED\r
+.equ ICR1H = 0x87 ; MEMORY MAPPED\r
+.equ TCNT1L = 0x84 ; MEMORY MAPPED\r
+.equ TCNT1H = 0x85 ; MEMORY MAPPED\r
+.equ TCCR1C = 0x82 ; MEMORY MAPPED\r
+.equ TCCR1B = 0x81 ; MEMORY MAPPED\r
+.equ TCCR1A = 0x80 ; MEMORY MAPPED\r
+.equ DIDR1 = 0x7f ; MEMORY MAPPED\r
+.equ DIDR0 = 0x7e ; MEMORY MAPPED\r
+.equ ADMUX = 0x7c ; MEMORY MAPPED\r
+.equ ADCSRB = 0x7b ; MEMORY MAPPED\r
+.equ ADCSRA = 0x7a ; MEMORY MAPPED\r
+.equ ADCH = 0x79 ; MEMORY MAPPED\r
+.equ ADCL = 0x78 ; MEMORY MAPPED\r
+.equ TIMSK2 = 0x70 ; MEMORY MAPPED\r
+.equ TIMSK1 = 0x6f ; MEMORY MAPPED\r
+.equ TIMSK0 = 0x6e ; MEMORY MAPPED\r
+.equ PCMSK1 = 0x6c ; MEMORY MAPPED\r
+.equ PCMSK2 = 0x6d ; MEMORY MAPPED\r
+.equ PCMSK0 = 0x6b ; MEMORY MAPPED\r
+.equ EICRA = 0x69 ; MEMORY MAPPED\r
+.equ PCICR = 0x68 ; MEMORY MAPPED\r
+.equ OSCCAL = 0x66 ; MEMORY MAPPED\r
+.equ PRR = 0x64 ; MEMORY MAPPED\r
+.equ CLKPR = 0x61 ; MEMORY MAPPED\r
+.equ WDTCSR = 0x60 ; MEMORY MAPPED\r
+.equ SREG = 0x3f\r
+.equ SPL = 0x3d\r
+.equ SPH = 0x3e\r
+.equ SPMCSR = 0x37\r
+.equ MCUCR = 0x35\r
+.equ MCUSR = 0x34\r
+.equ SMCR = 0x33\r
+.equ ACSR = 0x30\r
+.equ SPDR = 0x2e\r
+.equ SPSR = 0x2d\r
+.equ SPCR = 0x2c\r
+.equ GPIOR2 = 0x2b\r
+.equ GPIOR1 = 0x2a\r
+.equ OCR0B = 0x28\r
+.equ OCR0A = 0x27\r
+.equ TCNT0 = 0x26\r
+.equ TCCR0B = 0x25\r
+.equ TCCR0A = 0x24\r
+.equ GTCCR = 0x23\r
+.equ EEARH = 0x22\r
+.equ EEARL = 0x21\r
+.equ EEDR = 0x20\r
+.equ EECR = 0x1f\r
+.equ GPIOR0 = 0x1e\r
+.equ EIMSK = 0x1d\r
+.equ EIFR = 0x1c\r
+.equ PCIFR = 0x1b\r
+.equ TIFR2 = 0x17\r
+.equ TIFR1 = 0x16\r
+.equ TIFR0 = 0x15\r
+.equ PORTD = 0x0b\r
+.equ DDRD = 0x0a\r
+.equ PIND = 0x09\r
+.equ PORTC = 0x08\r
+.equ DDRC = 0x07\r
+.equ PINC = 0x06\r
+.equ PORTB = 0x05\r
+.equ DDRB = 0x04\r
+.equ PINB = 0x03\r
+\r
+\r
+; ***** BIT DEFINITIONS **************************************************\r
+\r
+; ***** USART0 ***********************\r
+; UDR0 - USART I/O Data Register\r
+.equ UDR0_0 = 0 ; USART I/O Data Register bit 0\r
+.equ UDR0_1 = 1 ; USART I/O Data Register bit 1\r
+.equ UDR0_2 = 2 ; USART I/O Data Register bit 2\r
+.equ UDR0_3 = 3 ; USART I/O Data Register bit 3\r
+.equ UDR0_4 = 4 ; USART I/O Data Register bit 4\r
+.equ UDR0_5 = 5 ; USART I/O Data Register bit 5\r
+.equ UDR0_6 = 6 ; USART I/O Data Register bit 6\r
+.equ UDR0_7 = 7 ; USART I/O Data Register bit 7\r
+\r
+; UCSR0A - USART Control and Status Register A\r
+.equ MPCM0 = 0 ; Multi-processor Communication Mode\r
+.equ U2X0 = 1 ; Double the USART transmission speed\r
+.equ UPE0 = 2 ; Parity Error\r
+.equ DOR0 = 3 ; Data overRun\r
+.equ FE0 = 4 ; Framing Error\r
+.equ UDRE0 = 5 ; USART Data Register Empty\r
+.equ TXC0 = 6 ; USART Transmitt Complete\r
+.equ RXC0 = 7 ; USART Receive Complete\r
+\r
+; UCSR0B - USART Control and Status Register B\r
+.equ TXB80 = 0 ; Transmit Data Bit 8\r
+.equ RXB80 = 1 ; Receive Data Bit 8\r
+.equ UCSZ02 = 2 ; Character Size\r
+.equ TXEN0 = 3 ; Transmitter Enable\r
+.equ RXEN0 = 4 ; Receiver Enable\r
+.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable\r
+.equ TXCIE0 = 6 ; TX Complete Interrupt Enable\r
+.equ RXCIE0 = 7 ; RX Complete Interrupt Enable\r
+\r
+; UCSR0C - USART Control and Status Register C\r
+.equ UCPOL0 = 0 ; Clock Polarity\r
+.equ UCSZ00 = 1 ; Character Size\r
+.equ UCPHA0 = UCSZ00 ; For compatibility\r
+.equ UCSZ01 = 2 ; Character Size\r
+.equ UDORD0 = UCSZ01 ; For compatibility\r
+.equ USBS0 = 3 ; Stop Bit Select\r
+.equ UPM00 = 4 ; Parity Mode Bit 0\r
+.equ UPM01 = 5 ; Parity Mode Bit 1\r
+.equ UMSEL00 = 6 ; USART Mode Select\r
+.equ UMSEL0 = UMSEL00 ; For compatibility\r
+.equ UMSEL01 = 7 ; USART Mode Select\r
+.equ UMSEL1 = UMSEL01 ; For compatibility\r
+\r
+; UBRR0H - USART Baud Rate Register High Byte\r
+.equ UBRR8 = 0 ; USART Baud Rate Register bit 8\r
+.equ UBRR9 = 1 ; USART Baud Rate Register bit 9\r
+.equ UBRR10 = 2 ; USART Baud Rate Register bit 10\r
+.equ UBRR11 = 3 ; USART Baud Rate Register bit 11\r
+\r
+; UBRR0L - USART Baud Rate Register Low Byte\r
+.equ UBRR0 = 0 ; USART Baud Rate Register bit 0\r
+.equ UBRR1 = 1 ; USART Baud Rate Register bit 1\r
+.equ UBRR2 = 2 ; USART Baud Rate Register bit 2\r
+.equ UBRR3 = 3 ; USART Baud Rate Register bit 3\r
+.equ UBRR4 = 4 ; USART Baud Rate Register bit 4\r
+.equ UBRR5 = 5 ; USART Baud Rate Register bit 5\r
+.equ UBRR6 = 6 ; USART Baud Rate Register bit 6\r
+.equ UBRR7 = 7 ; USART Baud Rate Register bit 7\r
+\r
+\r
+; ***** TWI **************************\r
+; TWAMR - TWI (Slave) Address Mask Register\r
+.equ TWAM0 = 1 ; \r
+.equ TWAMR0 = TWAM0 ; For compatibility\r
+.equ TWAM1 = 2 ; \r
+.equ TWAMR1 = TWAM1 ; For compatibility\r
+.equ TWAM2 = 3 ; \r
+.equ TWAMR2 = TWAM2 ; For compatibility\r
+.equ TWAM3 = 4 ; \r
+.equ TWAMR3 = TWAM3 ; For compatibility\r
+.equ TWAM4 = 5 ; \r
+.equ TWAMR4 = TWAM4 ; For compatibility\r
+.equ TWAM5 = 6 ; \r
+.equ TWAMR5 = TWAM5 ; For compatibility\r
+.equ TWAM6 = 7 ; \r
+.equ TWAMR6 = TWAM6 ; For compatibility\r
+\r
+; TWBR - TWI Bit Rate register\r
+.equ TWBR0 = 0 ; \r
+.equ TWBR1 = 1 ; \r
+.equ TWBR2 = 2 ; \r
+.equ TWBR3 = 3 ; \r
+.equ TWBR4 = 4 ; \r
+.equ TWBR5 = 5 ; \r
+.equ TWBR6 = 6 ; \r
+.equ TWBR7 = 7 ; \r
+\r
+; TWCR - TWI Control Register\r
+.equ TWIE = 0 ; TWI Interrupt Enable\r
+.equ TWEN = 2 ; TWI Enable Bit\r
+.equ TWWC = 3 ; TWI Write Collition Flag\r
+.equ TWSTO = 4 ; TWI Stop Condition Bit\r
+.equ TWSTA = 5 ; TWI Start Condition Bit\r
+.equ TWEA = 6 ; TWI Enable Acknowledge Bit\r
+.equ TWINT = 7 ; TWI Interrupt Flag\r
+\r
+; TWSR - TWI Status Register\r
+.equ TWPS0 = 0 ; TWI Prescaler\r
+.equ TWPS1 = 1 ; TWI Prescaler\r
+.equ TWS3 = 3 ; TWI Status\r
+.equ TWS4 = 4 ; TWI Status\r
+.equ TWS5 = 5 ; TWI Status\r
+.equ TWS6 = 6 ; TWI Status\r
+.equ TWS7 = 7 ; TWI Status\r
+\r
+; TWDR - TWI Data register\r
+.equ TWD0 = 0 ; TWI Data Register Bit 0\r
+.equ TWD1 = 1 ; TWI Data Register Bit 1\r
+.equ TWD2 = 2 ; TWI Data Register Bit 2\r
+.equ TWD3 = 3 ; TWI Data Register Bit 3\r
+.equ TWD4 = 4 ; TWI Data Register Bit 4\r
+.equ TWD5 = 5 ; TWI Data Register Bit 5\r
+.equ TWD6 = 6 ; TWI Data Register Bit 6\r
+.equ TWD7 = 7 ; TWI Data Register Bit 7\r
+\r
+; TWAR - TWI (Slave) Address register\r
+.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit\r
+.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0\r
+.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1\r
+.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2\r
+.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3\r
+.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4\r
+.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5\r
+.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6\r
+\r
+\r
+; ***** TIMER_COUNTER_1 **************\r
+; TIMSK1 - Timer/Counter Interrupt Mask Register\r
+.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable\r
+.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable\r
+.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable\r
+.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable\r
+\r
+; TIFR1 - Timer/Counter Interrupt Flag register\r
+.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag\r
+.equ OCF1A = 1 ; Output Compare Flag 1A\r
+.equ OCF1B = 2 ; Output Compare Flag 1B\r
+.equ ICF1 = 5 ; Input Capture Flag 1\r
+\r
+; TCCR1A - Timer/Counter1 Control Register A\r
+.equ WGM10 = 0 ; Waveform Generation Mode\r
+.equ WGM11 = 1 ; Waveform Generation Mode\r
+.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0\r
+.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1\r
+.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0\r
+.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1\r
+\r
+; TCCR1B - Timer/Counter1 Control Register B\r
+.equ CS10 = 0 ; Prescaler source of Timer/Counter 1\r
+.equ CS11 = 1 ; Prescaler source of Timer/Counter 1\r
+.equ CS12 = 2 ; Prescaler source of Timer/Counter 1\r
+.equ WGM12 = 3 ; Waveform Generation Mode\r
+.equ WGM13 = 4 ; Waveform Generation Mode\r
+.equ ICES1 = 6 ; Input Capture 1 Edge Select\r
+.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler\r
+\r
+; TCCR1C - Timer/Counter1 Control Register C\r
+.equ FOC1B = 6 ; \r
+.equ FOC1A = 7 ; \r
+\r
+; GTCCR - General Timer/Counter Control Register\r
+.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0\r
+.equ TSM = 7 ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** TIMER_COUNTER_2 **************\r
+; TIMSK2 - Timer/Counter Interrupt Mask register\r
+.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable\r
+.equ TOIE2A = TOIE2 ; For compatibility\r
+.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable\r
+.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable\r
+\r
+; TIFR2 - Timer/Counter Interrupt Flag Register\r
+.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag\r
+.equ OCF2A = 1 ; Output Compare Flag 2A\r
+.equ OCF2B = 2 ; Output Compare Flag 2B\r
+\r
+; TCCR2A - Timer/Counter2 Control Register A\r
+.equ WGM20 = 0 ; Waveform Genration Mode\r
+.equ WGM21 = 1 ; Waveform Genration Mode\r
+.equ COM2B0 = 4 ; Compare Output Mode bit 0\r
+.equ COM2B1 = 5 ; Compare Output Mode bit 1\r
+.equ COM2A0 = 6 ; Compare Output Mode bit 1\r
+.equ COM2A1 = 7 ; Compare Output Mode bit 1\r
+\r
+; TCCR2B - Timer/Counter2 Control Register B\r
+.equ CS20 = 0 ; Clock Select bit 0\r
+.equ CS21 = 1 ; Clock Select bit 1\r
+.equ CS22 = 2 ; Clock Select bit 2\r
+.equ WGM22 = 3 ; Waveform Generation Mode\r
+.equ FOC2B = 6 ; Force Output Compare B\r
+.equ FOC2A = 7 ; Force Output Compare A\r
+\r
+; TCNT2 - Timer/Counter2\r
+.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0\r
+.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1\r
+.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2\r
+.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3\r
+.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4\r
+.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5\r
+.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6\r
+.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7\r
+\r
+; OCR2A - Timer/Counter2 Output Compare Register A\r
+.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0\r
+.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1\r
+.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2\r
+.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3\r
+.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4\r
+.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5\r
+.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6\r
+.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7\r
+\r
+; OCR2B - Timer/Counter2 Output Compare Register B\r
+;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0\r
+;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1\r
+;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2\r
+;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3\r
+;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4\r
+;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5\r
+;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6\r
+;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7\r
+\r
+; ASSR - Asynchronous Status Register\r
+.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy\r
+.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy\r
+.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy\r
+.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy\r
+.equ TCN2UB = 4 ; Timer/Counter2 Update Busy\r
+.equ AS2 = 5 ; Asynchronous Timer/Counter2\r
+.equ EXCLK = 6 ; Enable External Clock Input\r
+\r
+; GTCCR - General Timer Counter Control register\r
+.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2\r
+.equ PSR2 = PSRASY ; For compatibility\r
+;.equ TSM = 7 ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** AD_CONVERTER *****************\r
+; ADMUX - The ADC multiplexer Selection Register\r
+.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits\r
+.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits\r
+.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits\r
+.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits\r
+.equ ADLAR = 5 ; Left Adjust Result\r
+.equ REFS0 = 6 ; Reference Selection Bit 0\r
+.equ REFS1 = 7 ; Reference Selection Bit 1\r
+\r
+; ADCSRA - The ADC Control and Status register A\r
+.equ ADPS0 = 0 ; ADC Prescaler Select Bits\r
+.equ ADPS1 = 1 ; ADC Prescaler Select Bits\r
+.equ ADPS2 = 2 ; ADC Prescaler Select Bits\r
+.equ ADIE = 3 ; ADC Interrupt Enable\r
+.equ ADIF = 4 ; ADC Interrupt Flag\r
+.equ ADATE = 5 ; ADC Auto Trigger Enable\r
+.equ ADSC = 6 ; ADC Start Conversion\r
+.equ ADEN = 7 ; ADC Enable\r
+\r
+; ADCSRB - The ADC Control and Status register B\r
+.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0\r
+.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1\r
+.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2\r
+.equ ACME = 6 ; \r
+\r
+; ADCH - ADC Data Register High Byte\r
+.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0\r
+.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1\r
+.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2\r
+.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3\r
+.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4\r
+.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5\r
+.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6\r
+.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7\r
+\r
+; ADCL - ADC Data Register Low Byte\r
+.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0\r
+.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1\r
+.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2\r
+.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3\r
+.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4\r
+.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5\r
+.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6\r
+.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7\r
+\r
+; DIDR0 - Digital Input Disable Register\r
+.equ ADC0D = 0 ; \r
+.equ ADC1D = 1 ; \r
+.equ ADC2D = 2 ; \r
+.equ ADC3D = 3 ; \r
+.equ ADC4D = 4 ; \r
+.equ ADC5D = 5 ; \r
+\r
+\r
+; ***** ANALOG_COMPARATOR ************\r
+; ACSR - Analog Comparator Control And Status Register\r
+.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0\r
+.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1\r
+.equ ACIC = 2 ; Analog Comparator Input Capture Enable\r
+.equ ACIE = 3 ; Analog Comparator Interrupt Enable\r
+.equ ACI = 4 ; Analog Comparator Interrupt Flag\r
+.equ ACO = 5 ; Analog Compare Output\r
+.equ ACBG = 6 ; Analog Comparator Bandgap Select\r
+.equ ACD = 7 ; Analog Comparator Disable\r
+\r
+; DIDR1 - Digital Input Disable Register 1\r
+.equ AIN0D = 0 ; AIN0 Digital Input Disable\r
+.equ AIN1D = 1 ; AIN1 Digital Input Disable\r
+\r
+\r
+; ***** PORTB ************************\r
+; PORTB - Port B Data Register\r
+.equ PORTB0 = 0 ; Port B Data Register bit 0\r
+.equ PB0 = 0 ; For compatibility\r
+.equ PORTB1 = 1 ; Port B Data Register bit 1\r
+.equ PB1 = 1 ; For compatibility\r
+.equ PORTB2 = 2 ; Port B Data Register bit 2\r
+.equ PB2 = 2 ; For compatibility\r
+.equ PORTB3 = 3 ; Port B Data Register bit 3\r
+.equ PB3 = 3 ; For compatibility\r
+.equ PORTB4 = 4 ; Port B Data Register bit 4\r
+.equ PB4 = 4 ; For compatibility\r
+.equ PORTB5 = 5 ; Port B Data Register bit 5\r
+.equ PB5 = 5 ; For compatibility\r
+.equ PORTB6 = 6 ; Port B Data Register bit 6\r
+.equ PB6 = 6 ; For compatibility\r
+.equ PORTB7 = 7 ; Port B Data Register bit 7\r
+.equ PB7 = 7 ; For compatibility\r
+\r
+; DDRB - Port B Data Direction Register\r
+.equ DDB0 = 0 ; Port B Data Direction Register bit 0\r
+.equ DDB1 = 1 ; Port B Data Direction Register bit 1\r
+.equ DDB2 = 2 ; Port B Data Direction Register bit 2\r
+.equ DDB3 = 3 ; Port B Data Direction Register bit 3\r
+.equ DDB4 = 4 ; Port B Data Direction Register bit 4\r
+.equ DDB5 = 5 ; Port B Data Direction Register bit 5\r
+.equ DDB6 = 6 ; Port B Data Direction Register bit 6\r
+.equ DDB7 = 7 ; Port B Data Direction Register bit 7\r
+\r
+; PINB - Port B Input Pins\r
+.equ PINB0 = 0 ; Port B Input Pins bit 0\r
+.equ PINB1 = 1 ; Port B Input Pins bit 1\r
+.equ PINB2 = 2 ; Port B Input Pins bit 2\r
+.equ PINB3 = 3 ; Port B Input Pins bit 3\r
+.equ PINB4 = 4 ; Port B Input Pins bit 4\r
+.equ PINB5 = 5 ; Port B Input Pins bit 5\r
+.equ PINB6 = 6 ; Port B Input Pins bit 6\r
+.equ PINB7 = 7 ; Port B Input Pins bit 7\r
+\r
+\r
+; ***** PORTC ************************\r
+; PORTC - Port C Data Register\r
+.equ PORTC0 = 0 ; Port C Data Register bit 0\r
+.equ PC0 = 0 ; For compatibility\r
+.equ PORTC1 = 1 ; Port C Data Register bit 1\r
+.equ PC1 = 1 ; For compatibility\r
+.equ PORTC2 = 2 ; Port C Data Register bit 2\r
+.equ PC2 = 2 ; For compatibility\r
+.equ PORTC3 = 3 ; Port C Data Register bit 3\r
+.equ PC3 = 3 ; For compatibility\r
+.equ PORTC4 = 4 ; Port C Data Register bit 4\r
+.equ PC4 = 4 ; For compatibility\r
+.equ PORTC5 = 5 ; Port C Data Register bit 5\r
+.equ PC5 = 5 ; For compatibility\r
+.equ PORTC6 = 6 ; Port C Data Register bit 6\r
+.equ PC6 = 6 ; For compatibility\r
+\r
+; DDRC - Port C Data Direction Register\r
+.equ DDC0 = 0 ; Port C Data Direction Register bit 0\r
+.equ DDC1 = 1 ; Port C Data Direction Register bit 1\r
+.equ DDC2 = 2 ; Port C Data Direction Register bit 2\r
+.equ DDC3 = 3 ; Port C Data Direction Register bit 3\r
+.equ DDC4 = 4 ; Port C Data Direction Register bit 4\r
+.equ DDC5 = 5 ; Port C Data Direction Register bit 5\r
+.equ DDC6 = 6 ; Port C Data Direction Register bit 6\r
+\r
+; PINC - Port C Input Pins\r
+.equ PINC0 = 0 ; Port C Input Pins bit 0\r
+.equ PINC1 = 1 ; Port C Input Pins bit 1\r
+.equ PINC2 = 2 ; Port C Input Pins bit 2\r
+.equ PINC3 = 3 ; Port C Input Pins bit 3\r
+.equ PINC4 = 4 ; Port C Input Pins bit 4\r
+.equ PINC5 = 5 ; Port C Input Pins bit 5\r
+.equ PINC6 = 6 ; Port C Input Pins bit 6\r
+\r
+\r
+; ***** PORTD ************************\r
+; PORTD - Port D Data Register\r
+.equ PORTD0 = 0 ; Port D Data Register bit 0\r
+.equ PD0 = 0 ; For compatibility\r
+.equ PORTD1 = 1 ; Port D Data Register bit 1\r
+.equ PD1 = 1 ; For compatibility\r
+.equ PORTD2 = 2 ; Port D Data Register bit 2\r
+.equ PD2 = 2 ; For compatibility\r
+.equ PORTD3 = 3 ; Port D Data Register bit 3\r
+.equ PD3 = 3 ; For compatibility\r
+.equ PORTD4 = 4 ; Port D Data Register bit 4\r
+.equ PD4 = 4 ; For compatibility\r
+.equ PORTD5 = 5 ; Port D Data Register bit 5\r
+.equ PD5 = 5 ; For compatibility\r
+.equ PORTD6 = 6 ; Port D Data Register bit 6\r
+.equ PD6 = 6 ; For compatibility\r
+.equ PORTD7 = 7 ; Port D Data Register bit 7\r
+.equ PD7 = 7 ; For compatibility\r
+\r
+; DDRD - Port D Data Direction Register\r
+.equ DDD0 = 0 ; Port D Data Direction Register bit 0\r
+.equ DDD1 = 1 ; Port D Data Direction Register bit 1\r
+.equ DDD2 = 2 ; Port D Data Direction Register bit 2\r
+.equ DDD3 = 3 ; Port D Data Direction Register bit 3\r
+.equ DDD4 = 4 ; Port D Data Direction Register bit 4\r
+.equ DDD5 = 5 ; Port D Data Direction Register bit 5\r
+.equ DDD6 = 6 ; Port D Data Direction Register bit 6\r
+.equ DDD7 = 7 ; Port D Data Direction Register bit 7\r
+\r
+; PIND - Port D Input Pins\r
+.equ PIND0 = 0 ; Port D Input Pins bit 0\r
+.equ PIND1 = 1 ; Port D Input Pins bit 1\r
+.equ PIND2 = 2 ; Port D Input Pins bit 2\r
+.equ PIND3 = 3 ; Port D Input Pins bit 3\r
+.equ PIND4 = 4 ; Port D Input Pins bit 4\r
+.equ PIND5 = 5 ; Port D Input Pins bit 5\r
+.equ PIND6 = 6 ; Port D Input Pins bit 6\r
+.equ PIND7 = 7 ; Port D Input Pins bit 7\r
+\r
+\r
+; ***** TIMER_COUNTER_0 **************\r
+; TIMSK0 - Timer/Counter0 Interrupt Mask Register\r
+.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable\r
+.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable\r
+.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable\r
+\r
+; TIFR0 - Timer/Counter0 Interrupt Flag register\r
+.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag\r
+.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A\r
+.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B\r
+\r
+; TCCR0A - Timer/Counter Control Register A\r
+.equ WGM00 = 0 ; Waveform Generation Mode\r
+.equ WGM01 = 1 ; Waveform Generation Mode\r
+.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm\r
+.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm\r
+.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode\r
+.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode\r
+\r
+; TCCR0B - Timer/Counter Control Register B\r
+.equ CS00 = 0 ; Clock Select\r
+.equ CS01 = 1 ; Clock Select\r
+.equ CS02 = 2 ; Clock Select\r
+.equ WGM02 = 3 ; \r
+.equ FOC0B = 6 ; Force Output Compare B\r
+.equ FOC0A = 7 ; Force Output Compare A\r
+\r
+; TCNT0 - Timer/Counter0\r
+.equ TCNT0_0 = 0 ; \r
+.equ TCNT0_1 = 1 ; \r
+.equ TCNT0_2 = 2 ; \r
+.equ TCNT0_3 = 3 ; \r
+.equ TCNT0_4 = 4 ; \r
+.equ TCNT0_5 = 5 ; \r
+.equ TCNT0_6 = 6 ; \r
+.equ TCNT0_7 = 7 ; \r
+\r
+; OCR0A - Timer/Counter0 Output Compare Register\r
+.equ OCROA_0 = 0 ; \r
+.equ OCROA_1 = 1 ; \r
+.equ OCROA_2 = 2 ; \r
+.equ OCROA_3 = 3 ; \r
+.equ OCROA_4 = 4 ; \r
+.equ OCROA_5 = 5 ; \r
+.equ OCROA_6 = 6 ; \r
+.equ OCROA_7 = 7 ; \r
+\r
+; OCR0B - Timer/Counter0 Output Compare Register\r
+.equ OCR0B_0 = 0 ; \r
+.equ OCR0B_1 = 1 ; \r
+.equ OCR0B_2 = 2 ; \r
+.equ OCR0B_3 = 3 ; \r
+.equ OCR0B_4 = 4 ; \r
+.equ OCR0B_5 = 5 ; \r
+.equ OCR0B_6 = 6 ; \r
+.equ OCR0B_7 = 7 ; \r
+\r
+; GTCCR - General Timer/Counter Control Register\r
+;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0\r
+.equ PSR10 = PSRSYNC ; For compatibility\r
+;.equ TSM = 7 ; Timer/Counter Synchronization Mode\r
+\r
+\r
+; ***** EXTERNAL_INTERRUPT ***********\r
+; EICRA - External Interrupt Control Register\r
+.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0\r
+.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1\r
+.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0\r
+.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1\r
+\r
+; EIMSK - External Interrupt Mask Register\r
+.equ INT0 = 0 ; External Interrupt Request 0 Enable\r
+.equ INT1 = 1 ; External Interrupt Request 1 Enable\r
+\r
+; EIFR - External Interrupt Flag Register\r
+.equ INTF0 = 0 ; External Interrupt Flag 0\r
+.equ INTF1 = 1 ; External Interrupt Flag 1\r
+\r
+; PCICR - Pin Change Interrupt Control Register\r
+.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0\r
+.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1\r
+.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2\r
+\r
+; PCMSK2 - Pin Change Mask Register 2\r
+.equ PCINT16 = 0 ; Pin Change Enable Mask 16\r
+.equ PCINT17 = 1 ; Pin Change Enable Mask 17\r
+.equ PCINT18 = 2 ; Pin Change Enable Mask 18\r
+.equ PCINT19 = 3 ; Pin Change Enable Mask 19\r
+.equ PCINT20 = 4 ; Pin Change Enable Mask 20\r
+.equ PCINT21 = 5 ; Pin Change Enable Mask 21\r
+.equ PCINT22 = 6 ; Pin Change Enable Mask 22\r
+.equ PCINT23 = 7 ; Pin Change Enable Mask 23\r
+\r
+; PCMSK1 - Pin Change Mask Register 1\r
+.equ PCINT8 = 0 ; Pin Change Enable Mask 8\r
+.equ PCINT9 = 1 ; Pin Change Enable Mask 9\r
+.equ PCINT10 = 2 ; Pin Change Enable Mask 10\r
+.equ PCINT11 = 3 ; Pin Change Enable Mask 11\r
+.equ PCINT12 = 4 ; Pin Change Enable Mask 12\r
+.equ PCINT13 = 5 ; Pin Change Enable Mask 13\r
+.equ PCINT14 = 6 ; Pin Change Enable Mask 14\r
+\r
+; PCMSK0 - Pin Change Mask Register 0\r
+.equ PCINT0 = 0 ; Pin Change Enable Mask 0\r
+.equ PCINT1 = 1 ; Pin Change Enable Mask 1\r
+.equ PCINT2 = 2 ; Pin Change Enable Mask 2\r
+.equ PCINT3 = 3 ; Pin Change Enable Mask 3\r
+.equ PCINT4 = 4 ; Pin Change Enable Mask 4\r
+.equ PCINT5 = 5 ; Pin Change Enable Mask 5\r
+.equ PCINT6 = 6 ; Pin Change Enable Mask 6\r
+.equ PCINT7 = 7 ; Pin Change Enable Mask 7\r
+\r
+; PCIFR - Pin Change Interrupt Flag Register\r
+.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0\r
+.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1\r
+.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2\r
+\r
+\r
+; ***** SPI **************************\r
+; SPDR - SPI Data Register\r
+.equ SPDR0 = 0 ; SPI Data Register bit 0\r
+.equ SPDR1 = 1 ; SPI Data Register bit 1\r
+.equ SPDR2 = 2 ; SPI Data Register bit 2\r
+.equ SPDR3 = 3 ; SPI Data Register bit 3\r
+.equ SPDR4 = 4 ; SPI Data Register bit 4\r
+.equ SPDR5 = 5 ; SPI Data Register bit 5\r
+.equ SPDR6 = 6 ; SPI Data Register bit 6\r
+.equ SPDR7 = 7 ; SPI Data Register bit 7\r
+\r
+; SPSR - SPI Status Register\r
+.equ SPI2X = 0 ; Double SPI Speed Bit\r
+.equ WCOL = 6 ; Write Collision Flag\r
+.equ SPIF = 7 ; SPI Interrupt Flag\r
+\r
+; SPCR - SPI Control Register\r
+.equ SPR0 = 0 ; SPI Clock Rate Select 0\r
+.equ SPR1 = 1 ; SPI Clock Rate Select 1\r
+.equ CPHA = 2 ; Clock Phase\r
+.equ CPOL = 3 ; Clock polarity\r
+.equ MSTR = 4 ; Master/Slave Select\r
+.equ DORD = 5 ; Data Order\r
+.equ SPE = 6 ; SPI Enable\r
+.equ SPIE = 7 ; SPI Interrupt Enable\r
+\r
+\r
+; ***** WATCHDOG *********************\r
+; WDTCSR - Watchdog Timer Control Register\r
+.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0\r
+.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1\r
+.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2\r
+.equ WDE = 3 ; Watch Dog Enable\r
+.equ WDCE = 4 ; Watchdog Change Enable\r
+.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3\r
+.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable\r
+.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag\r
+\r
+\r
+; ***** CPU **************************\r
+; SREG - Status Register\r
+.equ SREG_C = 0 ; Carry Flag\r
+.equ SREG_Z = 1 ; Zero Flag\r
+.equ SREG_N = 2 ; Negative Flag\r
+.equ SREG_V = 3 ; Two's Complement Overflow Flag\r
+.equ SREG_S = 4 ; Sign Bit\r
+.equ SREG_H = 5 ; Half Carry Flag\r
+.equ SREG_T = 6 ; Bit Copy Storage\r
+.equ SREG_I = 7 ; Global Interrupt Enable\r
+\r
+; OSCCAL - Oscillator Calibration Value\r
+.equ CAL0 = 0 ; Oscillator Calibration Value Bit0\r
+.equ CAL1 = 1 ; Oscillator Calibration Value Bit1\r
+.equ CAL2 = 2 ; Oscillator Calibration Value Bit2\r
+.equ CAL3 = 3 ; Oscillator Calibration Value Bit3\r
+.equ CAL4 = 4 ; Oscillator Calibration Value Bit4\r
+.equ CAL5 = 5 ; Oscillator Calibration Value Bit5\r
+.equ CAL6 = 6 ; Oscillator Calibration Value Bit6\r
+.equ CAL7 = 7 ; Oscillator Calibration Value Bit7\r
+\r
+; CLKPR - Clock Prescale Register\r
+.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0\r
+.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1\r
+.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2\r
+.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3\r
+.equ CLKPCE = 7 ; Clock Prescaler Change Enable\r
+\r
+; SPMCSR - Store Program Memory Control and Status Register\r
+.equ SELFPRGEN = 0 ; Self Programming Enable\r
+.equ PGERS = 1 ; Page Erase\r
+.equ PGWRT = 2 ; Page Write\r
+.equ BLBSET = 3 ; Boot Lock Bit Set\r
+.equ RWWSRE = 4 ; Read-While-Write section read enable\r
+.equ RWWSB = 6 ; Read-While-Write Section Busy\r
+.equ SPMIE = 7 ; SPM Interrupt Enable\r
+\r
+; MCUCR - MCU Control Register\r
+.equ IVCE = 0 ; \r
+.equ IVSEL = 1 ; \r
+.equ PUD = 4 ; \r
+.equ BODSE = 5 ; BOD Sleep Enable\r
+.equ BODS = 6 ; BOD Sleep\r
+\r
+; MCUSR - MCU Status Register\r
+.equ PORF = 0 ; Power-on reset flag\r
+.equ EXTRF = 1 ; External Reset Flag\r
+.equ EXTREF = EXTRF ; For compatibility\r
+.equ BORF = 2 ; Brown-out Reset Flag\r
+.equ WDRF = 3 ; Watchdog Reset Flag\r
+\r
+; SMCR - Sleep Mode Control Register\r
+.equ SE = 0 ; Sleep Enable\r
+.equ SM0 = 1 ; Sleep Mode Select Bit 0\r
+.equ SM1 = 2 ; Sleep Mode Select Bit 1\r
+.equ SM2 = 3 ; Sleep Mode Select Bit 2\r
+\r
+; GPIOR2 - General Purpose I/O Register 2\r
+.equ GPIOR20 = 0 ; \r
+.equ GPIOR21 = 1 ; \r
+.equ GPIOR22 = 2 ; \r
+.equ GPIOR23 = 3 ; \r
+.equ GPIOR24 = 4 ; \r
+.equ GPIOR25 = 5 ; \r
+.equ GPIOR26 = 6 ; \r
+.equ GPIOR27 = 7 ; \r
+\r
+; GPIOR1 - General Purpose I/O Register 1\r
+.equ GPIOR10 = 0 ; \r
+.equ GPIOR11 = 1 ; \r
+.equ GPIOR12 = 2 ; \r
+.equ GPIOR13 = 3 ; \r
+.equ GPIOR14 = 4 ; \r
+.equ GPIOR15 = 5 ; \r
+.equ GPIOR16 = 6 ; \r
+.equ GPIOR17 = 7 ; \r
+\r
+; GPIOR0 - General Purpose I/O Register 0\r
+.equ GPIOR00 = 0 ; \r
+.equ GPIOR01 = 1 ; \r
+.equ GPIOR02 = 2 ; \r
+.equ GPIOR03 = 3 ; \r
+.equ GPIOR04 = 4 ; \r
+.equ GPIOR05 = 5 ; \r
+.equ GPIOR06 = 6 ; \r
+.equ GPIOR07 = 7 ; \r
+\r
+; PRR - Power Reduction Register\r
+.equ PRADC = 0 ; Power Reduction ADC\r
+.equ PRUSART0 = 1 ; Power Reduction USART\r
+.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface\r
+.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1\r
+.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0\r
+.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2\r
+.equ PRTWI = 7 ; Power Reduction TWI\r
+\r
+\r
+; ***** EEPROM ***********************\r
+; EEARL - EEPROM Address Register Low Byte\r
+.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0\r
+.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1\r
+.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2\r
+.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3\r
+.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4\r
+.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5\r
+.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6\r
+.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7\r
+\r
+; EEARH - EEPROM Address Register High Byte\r
+.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8\r
+.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9\r
+\r
+; EEDR - EEPROM Data Register\r
+.equ EEDR0 = 0 ; EEPROM Data Register bit 0\r
+.equ EEDR1 = 1 ; EEPROM Data Register bit 1\r
+.equ EEDR2 = 2 ; EEPROM Data Register bit 2\r
+.equ EEDR3 = 3 ; EEPROM Data Register bit 3\r
+.equ EEDR4 = 4 ; EEPROM Data Register bit 4\r
+.equ EEDR5 = 5 ; EEPROM Data Register bit 5\r
+.equ EEDR6 = 6 ; EEPROM Data Register bit 6\r
+.equ EEDR7 = 7 ; EEPROM Data Register bit 7\r
+\r
+; EECR - EEPROM Control Register\r
+.equ EERE = 0 ; EEPROM Read Enable\r
+.equ EEPE = 1 ; EEPROM Write Enable\r
+.equ EEMPE = 2 ; EEPROM Master Write Enable\r
+.equ EERIE = 3 ; EEPROM Ready Interrupt Enable\r
+.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0\r
+.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1\r
+\r
+\r
+\r
+; ***** LOCKSBITS ********************************************************\r
+.equ LB1 = 0 ; Lock bit\r
+.equ LB2 = 1 ; Lock bit\r
+.equ BLB01 = 2 ; Boot Lock bit\r
+.equ BLB02 = 3 ; Boot Lock bit\r
+.equ BLB11 = 4 ; Boot lock bit\r
+.equ BLB12 = 5 ; Boot lock bit\r
+\r
+\r
+; ***** FUSES ************************************************************\r
+; LOW fuse bits\r
+.equ CKSEL0 = 0 ; Select Clock Source\r
+.equ CKSEL1 = 1 ; Select Clock Source\r
+.equ CKSEL2 = 2 ; Select Clock Source\r
+.equ CKSEL3 = 3 ; Select Clock Source\r
+.equ SUT0 = 4 ; Select start-up time\r
+.equ SUT1 = 5 ; Select start-up time\r
+.equ CKOUT = 6 ; Clock output\r
+.equ CKDIV8 = 7 ; Divide clock by 8\r
+\r
+; HIGH fuse bits\r
+.equ BOOTRST = 0 ; Select reset vector\r
+.equ BOOTSZ0 = 1 ; Select boot size\r
+.equ BOOTSZ1 = 2 ; Select boot size\r
+.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase\r
+.equ WDTON = 4 ; Watchdog Timer Always On\r
+.equ SPIEN = 5 ; Enable Serial programming and Data Downloading\r
+.equ DWEN = 6 ; debugWIRE Enable\r
+.equ RSTDISBL = 7 ; External reset disable\r
+\r
+; EXTENDED fuse bits\r
+.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level\r
+.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level\r
+.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level\r
+\r
+\r
+\r
+; ***** CPU REGISTER DEFINITIONS *****************************************\r
+.def XH = r27\r
+.def XL = r26\r
+.def YH = r29\r
+.def YL = r28\r
+.def ZH = r31\r
+.def ZL = r30\r
+\r
+\r
+\r
+; ***** DATA MEMORY DECLARATIONS *****************************************\r
+.equ FLASHEND = 0x3fff ; Note: Word address\r
+.equ IOEND = 0x00ff\r
+.equ SRAM_START = 0x0100\r
+.equ SRAM_SIZE = 2048\r
+.equ RAMEND = 0x08ff\r
+.equ XRAMEND = 0x0000\r
+.equ E2END = 0x03ff\r
+.equ EEPROMEND = 0x03ff\r
+.equ EEADRBITS = 10\r
+;#pragma AVRPART MEMORY PROG_FLASH 32768\r
+;#pragma AVRPART MEMORY EEPROM 1024\r
+;#pragma AVRPART MEMORY INT_SRAM SIZE 2048\r
+;#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100\r
+\r
+\r
+\r
+; ***** BOOTLOADER DECLARATIONS ******************************************\r
+.equ NRWW_START_ADDR = 0x3800\r
+.equ NRWW_STOP_ADDR = 0x3fff\r
+.equ RWW_START_ADDR = 0x0\r
+.equ RWW_STOP_ADDR = 0x37ff\r
+.equ PAGESIZE = 64\r
+.equ FIRSTBOOTSTART = 0x3f00\r
+.equ SECONDBOOTSTART = 0x3e00\r
+.equ THIRDBOOTSTART = 0x3c00\r
+.equ FOURTHBOOTSTART = 0x3800\r
+.equ SMALLBOOTSTART = FIRSTBOOTSTART\r
+.equ LARGEBOOTSTART = FOURTHBOOTSTART\r
+\r
+\r
+\r
+; ***** INTERRUPT VECTORS ************************************************\r
+.equ INT0addr = 0x0002 ; External Interrupt Request 0\r
+.equ INT1addr = 0x0004 ; External Interrupt Request 1\r
+.equ PCI0addr = 0x0006 ; Pin Change Interrupt Request 0\r
+.equ PCI1addr = 0x0008 ; Pin Change Interrupt Request 0\r
+.equ PCI2addr = 0x000a ; Pin Change Interrupt Request 1\r
+.equ WDTaddr = 0x000c ; Watchdog Time-out Interrupt\r
+.equ OC2Aaddr = 0x000e ; Timer/Counter2 Compare Match A\r
+.equ OC2Baddr = 0x0010 ; Timer/Counter2 Compare Match A\r
+.equ OVF2addr = 0x0012 ; Timer/Counter2 Overflow\r
+.equ ICP1addr = 0x0014 ; Timer/Counter1 Capture Event\r
+.equ OC1Aaddr = 0x0016 ; Timer/Counter1 Compare Match A\r
+.equ OC1Baddr = 0x0018 ; Timer/Counter1 Compare Match B\r
+.equ OVF1addr = 0x001a ; Timer/Counter1 Overflow\r
+.equ OC0Aaddr = 0x001c ; TimerCounter0 Compare Match A\r
+.equ OC0Baddr = 0x001e ; TimerCounter0 Compare Match B\r
+.equ OVF0addr = 0x0020 ; Timer/Couner0 Overflow\r
+.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete\r
+.equ URXCaddr = 0x0024 ; USART Rx Complete\r
+.equ UDREaddr = 0x0026 ; USART, Data Register Empty\r
+.equ UTXCaddr = 0x0028 ; USART Tx Complete\r
+.equ ADCCaddr = 0x002a ; ADC Conversion Complete\r
+.equ ERDYaddr = 0x002c ; EEPROM Ready\r
+.equ ACIaddr = 0x002e ; Analog Comparator\r
+.equ TWIaddr = 0x0030 ; Two-wire Serial Interface\r
+.equ SPMRaddr = 0x0032 ; Store Program Memory Read\r
+\r
+.equ INT_VECTORS_SIZE = 52 ; size in words\r
+\r
+#endif /* _M328PDEF_INC_ */\r
+\r
+; ***** END OF FILE ******************************************************\r
--- /dev/null
+; ------------------------------------------------------------------------------
+; siggen.asm
+;
+; Outputs digital samples in parallel on port D[7:0] pins
+; Momentary-close pushbutton on pin C5 cycles through waveforms
+; Analog voltage on pin ADC0 selects frequency
+; ------------------------------------------------------------------------------
+
+.include "./m328Pdef.inc"
+
+; ------------------------------------------------------------------------------
+; Configuration
+
+.equ STEP_MIN = 25 ; Minimum fractional steps through LUT per cycle
+.equ STEP_MAX = 2560 ; Maximum fractional steps through LUT per cycle
+
+
+; ------------------------------------------------------------------------------
+; Registers
+
+; r0 ----- Multiplication temp
+; r1 ----- Multiplication temp
+; r2 ----- Multiplication temp
+; r3 ----- Multiplication temp
+; r4 ----- Multiplication temp
+; r5 ----- Multiplication temp
+; r6 ----- Multiplication temp
+; r7 ----- Multiplication temp
+; r8
+; r9
+; r10
+; r11
+; r12
+; r13
+; r14 ----- Saved SREG (hare kernel clobbers flags)
+; r15 ----- Hare kernel temporary
+; r16 l\_ Step size within waveform LUT (8.8 fixed point)
+; r17 h/
+; r18
+; r19 ----- Zero for adding carry
+; r20 l\_ Multiplier during scaling
+; r21 h/
+; r22
+; r23 ----- Fractional part of pointer to current sample within waveform table
+; r24 ----- Second temporary
+; r25 ----- First temporary
+; r26 l\_X (X) Pointer to current sample within waveform table
+; r27 h/
+; r28 l\_Y
+; r29 h/
+; r30 l\_Z (Z) Pointer to next waveform table in rom
+; r31 h/
+
+
+; ------------------------------------------------------------------------------
+; Hare kernel
+
+; There are two separate "things" that need to be done repeatedly in this code,
+; which I'll be calling "loop kernels":
+;
+; - Handle user input (waveform select button and frequency knob)
+; - Output a sample from the waveform LUT
+;
+; User input handling can happen on a liesurely timescale (at the very least
+; once every 200ms (5 Hz), and precise timing is not necessary)
+;
+; Sample output must happen as quickly as possible and with a fixed number of
+; clock cycles between samples to prevent phase noise.
+;
+; I call these the "tortoise" and "hare" kernels, respectively. The tortoise
+; kernel makes up the main loop body, and it is split into 3-clock-cycle chunks
+; with the hare kernel being run in between each chunk.
+;
+; Care must be taken to avoid register conflicts (including flags in SREG!)
+;
+; With 3-cycle tortoise chunks and a 5-cycle hare kernel, we can output samples
+; with only 8 clock cycles between them. With a 16 MHz clock, that yields
+; 2 MSPS.
+
+.macro HARE_KERNEL
+ ; ----- Output a sample
+ ld r15, X ; 2
+ out PORTD, r15 ; 1
+
+ ; ----- Advance the sample pointer
+ add r23, r16 ; 1 Fractional part
+ adc XL, r17 ; 1 Integer low part (do not carry to high part)
+.endmacro
+
+
+; ------------------------------------------------------------------------------
+; Interrupt vector table
+
+.cseg
+
+.org 0x0000
+ rjmp reset ; RESET
+ reti
+ reti ; INT0
+ reti
+ reti ; INT1
+ reti
+ reti ; PCINT0
+ reti
+ reti ; PCINT1
+ reti
+ reti ; PCINT2
+ reti
+ reti ; WDT
+ reti
+ reti ; TIMER2 COMPA
+ reti
+ reti ; TIMER2 COMPB
+ reti
+ reti ; TIMER2 OVF
+ reti
+ reti ; TIMER1 CAPT
+ reti
+ reti ; TIMER1 COMPA
+ reti
+ reti ; TIMER1 COMPB
+ reti
+ reti ; TIMER1 OVF
+ reti
+ reti ; TIMER0 COMPA
+ reti
+ reti ; TIMER0 COMPB
+ reti
+ reti ; TIMER0 OVF
+ reti
+ reti ; SPI, STC
+ reti
+ reti ; USART, RX
+ reti
+ reti ; USART, UDRE
+ reti
+ reti ; USART, TX
+ reti
+ reti ; ADC
+ reti
+ reti ; EE READY
+ reti
+ reti ; ANALOG COMP
+ reti
+ reti ; TWI
+ reti
+ reti ; SPM READY
+ reti
+
+
+; ------------------------------------------------------------------------------
+; Reset entry point
+
+reset:
+ ; ----- Disable interrupts and set stack pointer to top of SRAM
+
+ eor r25, r25
+ out SREG, r25
+ ldi r25, HIGH(RAMEND)
+ out SPH, r25
+ ldi r25, LOW(RAMEND)
+ out SPL, r25
+
+ ; ----- Set up PORTD for outputting samples, initial output to center of range
+
+ ldi r25, 0x80
+ out PORTD, r25
+ ldi r25, 0xff
+ out DDRD, r25
+
+ ; ----- Set up ADC for reading the frequency knob
+
+ ; ADEN <= 1 Enable ADC
+ ; ADSC <= 0 Do not start conversion
+ ; ADATE <= 0 Do not autotrigger
+ ; ADIF <= 1 Clear any pending interrupt flags (just in case)
+ ; ADIE <= 0 Disable ADC interrupts (we will poll ADIF)
+ ; ADPS <= 7 System clock 16MHz, ADC requres <= 200kHz, scale by 128
+ ldi r25, (1 << ADEN) | \
+ (0 << ADSC) | \
+ (0 << ADATE) | \
+ (1 << ADIF) | \
+ (0 << ADIE) | \
+ (7 << ADPS0)
+ sts ADCSRA, r25
+
+ ; REFS <= 0 Use AREF as reference
+ ; ADLAR <= 0 Do not left-justify results
+ ; MUX <= 0 Select input ADC0
+ ldi r25, (0 << REFS0) | \
+ (0 << ADLAR) | \
+ (0 << MUX0)
+ sts ADMUX, r25
+
+ ; ADCSRB is for the comparator and autotrigger, neither are active
+
+ ; ----- Set up button pin and timer for switching waveforms
+
+ ; Set PORTC5 as input with pullup
+ cbi DDRC, DDC5
+ sbi PORTC, PORTC5
+
+ ; Allow PCINT13 (button) to trigger pin change interrupts
+ ldi r25, (1 << PCINT13)
+ sts PCMSK1, r25
+
+ ; Clear any existing pin interrupts
+ in r25, PCIFR
+ out PCIFR, r25
+
+ ; No need to set PCCSR bits since we won't actually be getting
+ ; interrupted, and PCISR bits will be set regardless
+
+ ; Hold prescaler in reset so timer remains halted until we need it
+ ldi r25, (1 << TSM) | \
+ (1 << PSRSYNC)
+ out GTCCR, r25
+
+ ; Timer 0: CTC mode (reset after compare match)
+ ; Clock source CLK_io / 64
+ ldi r25, (1 << WGM01) | \
+ (0 << WGM00)
+ out TCCR0A, r25
+ ldi r25, (0 << WGM02) | \
+ (3 << CS00)
+ out TCCR0B, r25
+ sbi TIFR0, OCF0A ; Make sure the timer flag is clear
+ ldi r25, 250 ; Count up to 250 (at 16MHz/64 = 250kHz -> 1ms)
+ out OCR0A, r25
+ ldi r25, 0 ; Reset the timer counter
+ out TCNT0, r25
+
+ ; ----- Set up the initial waveform
+
+ ; Point Z at the first waveform in the rom
+ ldi ZL, LOW(2*wavetable_begin)
+ ldi ZH, HIGH(2*wavetable_begin)
+
+ ; Advance waveforms to load the LUT into ram and reset the cursor
+ rcall next_waveform
+
+ ; Initial step size
+ ldi r16, LOW(STEP_MAX);0x00 ; Fractional part
+ ldi r17, HIGH(STEP_MAX);0x04 ; Integer part
+
+ ; --------------------------------------------------------------
+ ; Main loop
+loop:
+ ; --------------------------------------------------------------
+ ; ----- Read the frequency knob
+
+ ; Trigger a single conversion
+ HARE_KERNEL
+ lds r25, ADCSRA ; 2
+ ori r25, (1 << ADSC) ; 1
+ HARE_KERNEL
+ sts ADCSRA, r25 ; 2
+ nop ; 1
+
+ ; Wait for conversion to complete
+_adc_wait:
+ HARE_KERNEL
+ lds r25, ADCSRA ; 2
+ nop ; 1
+ HARE_KERNEL
+ sbrs r25, ADIF ; 1/2 Test for interrupt flag
+ rjmp _adc_wait ; 2
+ nop ; 1
+ HARE_KERNEL
+ sts ADCSRA, r25 ; 2 Store back to clear the interrupt flag (w1c)
+ nop ; 1
+
+ ; Read value from ADC
+ HARE_KERNEL
+ lds r24, ADCL ; 2
+ nop ; 1
+ HARE_KERNEL
+ lds r25, ADCH ; 2
+ nop ; 1
+
+ ; --------------------------------------------------------------
+ ; ----- Compute step size
+ ;
+ ; Map V in range (ADC_MIN, ADC_MAX) to (STEP_MIN, STEP_MAX)
+ ;
+ ; / (STEP_MAX - STEP_MIN) \
+ ; X = | (V - ADC_MIN) * --------------------- | + STEP_MIN
+ ; \ (ADC_MAX - ADC_MIN) /
+ ;
+ ; ADC_MIN = 0 and ADC_MAX = 1023 (~1024), so this can be simplified
+ ;
+ ; We do V * (STEP_MAX - STEP_MIN) first to avoid losing precision
+ ; Then divide by (ADC_MAX - ADC_MIN) by shifting right 10 bits
+ ; (Which we do by dropping the least-significant byte and shifting 2)
+ ;
+ ; 16-bit multiplication from 8-bit multiplications
+ ; Like multiplying two two-digit numbers, but each "digit" is now a byte
+ ;
+ ; r25 r24
+ ; A B <- value from ADC
+ ; r21 r20
+ ; * C D <- scale factor (STEP_MAX - STEP_MIN)
+ ; ------------
+ ; r7 r6
+ ; DBH DBL
+ ; r5 r4
+ ; DAH DAL
+ ; r3 r2
+ ; CBH CBL
+ ; r1 r0
+ ; + CAH CAL
+ ; ---------------------
+ ; r1 r0 r2 r6 <- 32-bit result
+
+ ; Get variables ready
+ HARE_KERNEL
+ ldi r19, 0x00 ; 1
+ ldi r20, LOW(STEP_MAX - STEP_MIN) ; 1
+ ldi r21, HIGH(STEP_MAX - STEP_MIN) ; 1
+
+ ; Generate partial products
+ HARE_KERNEL
+ mul r20, r24 ; 2
+ movw r6, r0 ; 1
+ HARE_KERNEL
+ mul r20, r25 ; 2
+ movw r4, r0 ; 1
+ HARE_KERNEL
+ mul r21, r24 ; 2
+ movw r2, r0 ; 1
+ HARE_KERNEL
+ mul r21, r25 ; 2
+ nop ; 1
+
+ ; Add partial products
+ HARE_KERNEL
+ add r4, r7 ; 1
+ adc r3, r5 ; 1
+ in r14, SREG ; 1 Save carry flag
+ HARE_KERNEL
+ out SREG, r14 ; 1 Restore carry flag
+ adc r1, r19 ; 1 Carry only
+ nop ; 1
+ HARE_KERNEL
+ add r2, r4 ; 1
+ adc r0, r3 ; 1
+ in r14, SREG ; 1 Save carry flag
+ HARE_KERNEL
+ out SREG, r14 ; 1 Restore carry flag
+ adc r1, r19 ; 1 Carry only
+ nop ; 1
+ ; Full 32-bit product is in r1:r0:r2:r6
+
+ ; Shift down by 10 for division by 1024 (discard r6, shift 2)
+ HARE_KERNEL
+ clc ; 1
+ ror r1 ; 1
+ in r14, SREG ; 1 Save carry flag
+ HARE_KERNEL
+ out SREG, r14 ; 1 Restore carry flag
+ ror r0 ; 1
+ ror r2 ; 1
+ HARE_KERNEL
+ clc ; 1
+ ror r1 ; 1
+ in r14, SREG ; 1 Save carry flag
+ HARE_KERNEL
+ out SREG, r14 ; 1 Restore carry flag
+ ror r0 ; 1
+ ror r2 ; 1
+
+ ; Add offset
+ HARE_KERNEL
+ mov r24, r2 ; 1
+ mov r25, r0 ; 1
+ nop ; 1
+ HARE_KERNEL
+ adiw r24, STEP_MIN ; 2
+
+ ; Copy into step size variable
+ movw r16, r24 ; 1
+
+ ; --------------------------------------------------------------
+ ; ----- Poll for button presses and swap waveforms
+
+ HARE_KERNEL
+ sbic PINC, PINC5 ; 1/2
+ rjmp loop ; 2
+
+ ; Button pin status has changed
+
+ ; Timing is no longer important, as we do not run the hare kernel here
+
+ ; Advance to next waveform in rom and copy to waveform LUT
+ ; Do this before the switch debouncing so the time spent copying can be
+ ; used as part of the wait time for the switch to settle
+ rcall next_waveform
+
+ ; Debounce, wait for button release, and debounce again
+ rcall debounce
+_button_wait_release:
+ sbis PINC, PINC5
+ rjmp _button_wait_release
+ rcall debounce
+ rjmp loop
+
+
+; ------------------------------------------------------------------------------
+; Subroutines
+
+next_waveform:
+ ; Throughout execution, Z points to the next wavetable to be loaded into
+ ; the waveform buffer. This subroutine advances the Z pointer as it
+ ; copies, and wraps it back around to the beginning of the wavetable if
+ ; it reaches the end.
+
+ ; Copy the next waveform from the wavetable ROM into the waveform buffer
+ ldi XL, LOW(waveform) ; Point X at the waveform buffer
+ ldi XH, HIGH(waveform)
+ ldi r25, 0x00
+_next_waveform_loop:
+ lpm r24, Z+ ; Load a byte from wavetale
+ st X+, r24 ; Store it to the waveform buffer
+ inc r25 ; Advance counter
+ brne _next_waveform_loop ; Exit when counter overflows to zero
+
+ ; Handle wrap-around after cycling through all waveforms
+ ; Waveforms are all 256 bytes long, so the lower byte of Z will always
+ ; be the same after copying, so no need to reload it
+ cpi ZH, HIGH(2*wavetable_end) ; Did we copy the final waveform?
+ brne _next_waveform_nowrap
+ ldi ZH, HIGH(2*wavetable_begin) ; If so, reset to the first waveform
+_next_waveform_nowrap:
+
+ ; Reset the current sample pointer
+ ldi r23, 0x00 ; Fractional part
+ ldi XL, LOW(waveform) ; Integer low part
+ ldi XH, HIGH(waveform) ; Integer high part
+
+ ret
+
+
+debounce:
+ ; Debouncing is done by waiting for the pin to be quiet (no transitions)
+ ; for some specified amount of time (1ms for now, see OCR0A in the init
+ ; section above).
+ ;
+ ; We run the timer for 1ms and run in a busyloop until it expires. If
+ ; during this loop the pin change flag indicates that there was a
+ ; transition, we reset the timer and wait again.
+
+_debounce_reset:
+ sbi PCIFR, PCIF1 ; Ensure pin change flag is cleared (w1c)
+ sbi TIFR0, OCF0A ; Ensure timer expire flag is cleared (w1c)
+
+ ; PSRSYNC resets the timer clock prescaler
+ ; TSM forces the prescaler to be held in reset
+ ldi r25, (1 << TSM) | \
+ (1 << PSRSYNC)
+ out GTCCR, r25 ; Reset the prescaler and halt
+ ldi r25, 0x00
+ out TCNT0, r25 ; Reset timer count value
+ out GTCCR, r25 ; Unhalt the prescaler to run the timer
+_debounce_busyloop:
+ sbic PCIFR, PCIF1 ; If the pin changed again, reset and retry
+ rjmp _debounce_reset
+ sbis TIFR0, OCF0A ; IF the timer expired, exit the loop
+ rjmp _debounce_busyloop
+
+ ret
+
+
+; ------------------------------------------------------------------------------
+; Waveform data
+
+.dseg
+
+; Waveform table must be 256-byte aligned
+; (The assembler appears to lack an "align" directive!)
+.org 0x100
+waveform:
+ .byte 256
+
+.cseg
+
+; Waveform data must be contiguous
+wavetable_begin:
+; Sine
+ .db 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x95
+ .db 0x98, 0x9c, 0x9f, 0xa2, 0xa5, 0xa8, 0xab, 0xae
+ .db 0xb0, 0xb3, 0xb6, 0xb9, 0xbc, 0xbf, 0xc1, 0xc4
+ .db 0xc7, 0xc9, 0xcc, 0xce, 0xd1, 0xd3, 0xd5, 0xd8
+ .db 0xda, 0xdc, 0xde, 0xe0, 0xe2, 0xe4, 0xe6, 0xe8
+ .db 0xea, 0xec, 0xed, 0xef, 0xf0, 0xf2, 0xf3, 0xf5
+ .db 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfc
+ .db 0xfd, 0xfe, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe
+ .db 0xfd, 0xfc, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8, 0xf7
+ .db 0xf6, 0xf5, 0xf3, 0xf2, 0xf0, 0xef, 0xed, 0xec
+ .db 0xea, 0xe8, 0xe6, 0xe4, 0xe2, 0xe0, 0xde, 0xdc
+ .db 0xda, 0xd8, 0xd5, 0xd3, 0xd1, 0xce, 0xcc, 0xc9
+ .db 0xc7, 0xc4, 0xc1, 0xbf, 0xbc, 0xb9, 0xb6, 0xb3
+ .db 0xb0, 0xae, 0xab, 0xa8, 0xa5, 0xa2, 0x9f, 0x9c
+ .db 0x98, 0x95, 0x92, 0x8f, 0x8c, 0x89, 0x86, 0x83
+ .db 0x80, 0x7c, 0x79, 0x76, 0x73, 0x70, 0x6d, 0x6a
+ .db 0x67, 0x63, 0x60, 0x5d, 0x5a, 0x57, 0x54, 0x51
+ .db 0x4f, 0x4c, 0x49, 0x46, 0x43, 0x40, 0x3e, 0x3b
+ .db 0x38, 0x36, 0x33, 0x31, 0x2e, 0x2c, 0x2a, 0x27
+ .db 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17
+ .db 0x15, 0x13, 0x12, 0x10, 0x0f, 0x0d, 0x0c, 0x0a
+ .db 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x03
+ .db 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01
+ .db 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
+ .db 0x09, 0x0a, 0x0c, 0x0d, 0x0f, 0x10, 0x12, 0x13
+ .db 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23
+ .db 0x25, 0x27, 0x2a, 0x2c, 0x2e, 0x31, 0x33, 0x36
+ .db 0x38, 0x3b, 0x3e, 0x40, 0x43, 0x46, 0x49, 0x4c
+ .db 0x4f, 0x51, 0x54, 0x57, 0x5a, 0x5d, 0x60, 0x63
+ .db 0x67, 0x6a, 0x6d, 0x70, 0x73, 0x76, 0x79, 0x7c
+
+; Square
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+; Rising sawtooth
+ .db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
+ .db 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
+ .db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17
+ .db 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
+ .db 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27
+ .db 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f
+ .db 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37
+ .db 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f
+ .db 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47
+ .db 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f
+ .db 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57
+ .db 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
+ .db 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67
+ .db 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f
+ .db 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77
+ .db 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f
+ .db 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87
+ .db 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f
+ .db 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97
+ .db 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f
+ .db 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7
+ .db 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf
+ .db 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7
+ .db 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf
+ .db 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7
+ .db 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf
+ .db 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7
+ .db 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf
+ .db 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7
+ .db 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef
+ .db 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7
+ .db 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
+
+; Falling sawtooth
+ .db 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8
+ .db 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0
+ .db 0xef, 0xee, 0xed, 0xec, 0xeb, 0xea, 0xe9, 0xe8
+ .db 0xe7, 0xe6, 0xe5, 0xe4, 0xe3, 0xe2, 0xe1, 0xe0
+ .db 0xdf, 0xde, 0xdd, 0xdc, 0xdb, 0xda, 0xd9, 0xd8
+ .db 0xd7, 0xd6, 0xd5, 0xd4, 0xd3, 0xd2, 0xd1, 0xd0
+ .db 0xcf, 0xce, 0xcd, 0xcc, 0xcb, 0xca, 0xc9, 0xc8
+ .db 0xc7, 0xc6, 0xc5, 0xc4, 0xc3, 0xc2, 0xc1, 0xc0
+ .db 0xbf, 0xbe, 0xbd, 0xbc, 0xbb, 0xba, 0xb9, 0xb8
+ .db 0xb7, 0xb6, 0xb5, 0xb4, 0xb3, 0xb2, 0xb1, 0xb0
+ .db 0xaf, 0xae, 0xad, 0xac, 0xab, 0xaa, 0xa9, 0xa8
+ .db 0xa7, 0xa6, 0xa5, 0xa4, 0xa3, 0xa2, 0xa1, 0xa0
+ .db 0x9f, 0x9e, 0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98
+ .db 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90
+ .db 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88
+ .db 0x87, 0x86, 0x85, 0x84, 0x83, 0x82, 0x81, 0x80
+ .db 0x7f, 0x7e, 0x7d, 0x7c, 0x7b, 0x7a, 0x79, 0x78
+ .db 0x77, 0x76, 0x75, 0x74, 0x73, 0x72, 0x71, 0x70
+ .db 0x6f, 0x6e, 0x6d, 0x6c, 0x6b, 0x6a, 0x69, 0x68
+ .db 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x61, 0x60
+ .db 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 0x59, 0x58
+ .db 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50
+ .db 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48
+ .db 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40
+ .db 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38
+ .db 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30
+ .db 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28
+ .db 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20
+ .db 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18
+ .db 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10
+ .db 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08
+ .db 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
+
+; Triangle
+ .db 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e
+ .db 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e
+ .db 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e
+ .db 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e
+ .db 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e
+ .db 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e
+ .db 0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e
+ .db 0x70, 0x72, 0x74, 0x76, 0x78, 0x7a, 0x7c, 0x7e
+ .db 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e
+ .db 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e
+ .db 0xa0, 0xa2, 0xa4, 0xa6, 0xa8, 0xaa, 0xac, 0xae
+ .db 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe
+ .db 0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce
+ .db 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde
+ .db 0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee
+ .db 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe
+ .db 0xff, 0xfd, 0xfb, 0xf9, 0xf7, 0xf5, 0xf3, 0xf1
+ .db 0xef, 0xed, 0xeb, 0xe9, 0xe7, 0xe5, 0xe3, 0xe1
+ .db 0xdf, 0xdd, 0xdb, 0xd9, 0xd7, 0xd5, 0xd3, 0xd1
+ .db 0xcf, 0xcd, 0xcb, 0xc9, 0xc7, 0xc5, 0xc3, 0xc1
+ .db 0xbf, 0xbd, 0xbb, 0xb9, 0xb7, 0xb5, 0xb3, 0xb1
+ .db 0xaf, 0xad, 0xab, 0xa9, 0xa7, 0xa5, 0xa3, 0xa1
+ .db 0x9f, 0x9d, 0x9b, 0x99, 0x97, 0x95, 0x93, 0x91
+ .db 0x8f, 0x8d, 0x8b, 0x89, 0x87, 0x85, 0x83, 0x81
+ .db 0x7f, 0x7d, 0x7b, 0x79, 0x77, 0x75, 0x73, 0x71
+ .db 0x6f, 0x6d, 0x6b, 0x69, 0x67, 0x65, 0x63, 0x61
+ .db 0x5f, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51
+ .db 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41
+ .db 0x3f, 0x3d, 0x3b, 0x39, 0x37, 0x35, 0x33, 0x31
+ .db 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 0x23, 0x21
+ .db 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11
+ .db 0x0f, 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01
+
+; White noise, contains all values 0-255, randomized
+ .db 0x7a, 0x1b, 0x50, 0xac, 0xa6, 0xf7, 0xf1, 0x82
+ .db 0x6d, 0xfc, 0x24, 0x5d, 0x6e, 0xe9, 0xd6, 0x74
+ .db 0x08, 0x8e, 0x28, 0xf6, 0x13, 0x22, 0xd3, 0xb1
+ .db 0x60, 0x5c, 0x67, 0x21, 0xca, 0x01, 0x72, 0x2f
+ .db 0xd8, 0xeb, 0x32, 0x3a, 0x88, 0x81, 0x83, 0x59
+ .db 0x7d, 0x5b, 0x2a, 0x87, 0x5f, 0x99, 0x96, 0x09
+ .db 0xef, 0xd5, 0x2c, 0x17, 0x94, 0x8c, 0xff, 0xdd
+ .db 0x57, 0xe5, 0x0a, 0xf5, 0x10, 0xaf, 0x36, 0x2e
+ .db 0x4b, 0x35, 0xc4, 0xb0, 0xf0, 0x61, 0xab, 0x95
+ .db 0x18, 0x26, 0x9e, 0x7f, 0x33, 0x65, 0x9c, 0x70
+ .db 0xbf, 0xa7, 0x64, 0xc3, 0x1a, 0x31, 0xee, 0xc8
+ .db 0x14, 0x25, 0x76, 0xc6, 0x58, 0x52, 0x03, 0x9b
+ .db 0x1f, 0xdf, 0x0f, 0xc1, 0x42, 0x68, 0x27, 0xe0
+ .db 0x2b, 0x54, 0xd0, 0xfa, 0x4e, 0x93, 0xa5, 0xf2
+ .db 0x05, 0x3b, 0x1d, 0x02, 0xf8, 0xea, 0x45, 0x4a
+ .db 0x04, 0xcb, 0xf9, 0xc5, 0x7c, 0xe4, 0x48, 0x1c
+ .db 0xae, 0x75, 0xbe, 0xb4, 0x9f, 0xd9, 0x37, 0x11
+ .db 0x46, 0xcd, 0x3f, 0xe2, 0x9a, 0xe1, 0x9d, 0xb2
+ .db 0xc0, 0xb3, 0xa3, 0x77, 0x34, 0x80, 0xfd, 0x1e
+ .db 0xa1, 0xed, 0x07, 0x6c, 0x30, 0x6a, 0x69, 0x97
+ .db 0x23, 0xd7, 0x3e, 0xde, 0x4f, 0x79, 0x8b, 0x4d
+ .db 0xc2, 0xb6, 0x84, 0xa4, 0x66, 0xd1, 0xba, 0x0c
+ .db 0xf4, 0xbc, 0x8f, 0xd4, 0x40, 0xdb, 0xaa, 0xcf
+ .db 0x8a, 0x56, 0xad, 0x7b, 0x0e, 0x3c, 0xc7, 0x71
+ .db 0xfb, 0x49, 0x90, 0x98, 0x5e, 0xf3, 0x12, 0x38
+ .db 0x00, 0xe3, 0x0b, 0xec, 0x55, 0x39, 0x89, 0xbb
+ .db 0x78, 0x91, 0x15, 0x51, 0xe6, 0x47, 0x43, 0x0d
+ .db 0xa9, 0xb9, 0x6b, 0x62, 0x73, 0xa0, 0xdc, 0x2d
+ .db 0xe8, 0x63, 0xda, 0xd2, 0xfe, 0xc9, 0x29, 0xa2
+ .db 0x20, 0x8d, 0x53, 0xa8, 0x19, 0x4c, 0x6f, 0x86
+ .db 0xce, 0x92, 0x06, 0xe7, 0x7e, 0xb8, 0x5a, 0x3d
+ .db 0xb5, 0x85, 0x44, 0x16, 0xb7, 0xcc, 0x41, 0xbd
+wavetable_end:
+
projects / atmega / siggen.git / commitdiff