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(parent: ba4f31a) | patch

author	rs <>
	Sat, 13 Dec 2025 04:41:25 +0000 (22:41 -0600)
committer	rs <>
	Sat, 13 Dec 2025 04:41:25 +0000 (22:41 -0600)
commit	f7dd63c40c40469e36612ea3ed60ea8b1f077176
tree	aa8ffb0889bd400f043cbf4c4bdb91606768d7ca	tree \| snapshot
parent	ba4f31a95d9f026cfbf24c6dbe7da530daa22e17	commit \| diff

Update enable logic and add reset to pipectrl

libraries/dsp/pipectrl.vhd		diff \| blob \| history
libraries/dsp/pipectrl_runout.vhd		diff \| blob \| history
libraries/dsp/pipectrl_runout_srl.vhd		diff \| blob \| history

All of my VHDL libraries and projects