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(parent: f3fc081) | patch
Add clock domain crossers
authorrs <>
Tue, 11 Nov 2025 21:01:29 +0000 (15:01 -0600)
committerrs <>
Tue, 11 Nov 2025 21:01:29 +0000 (15:01 -0600)
commit3eb3a187fe4e42698470a2011c4f9c4e15431bb1
tree5e940242ae5fde1192457a3c56936df4f52c3d6ftree | snapshot
parentf3fc0816ec0c9dd3ac79d67de3c8a662b0e37baccommit | diff
Add clock domain crossers

This is an initial commit, but there are some problems here.

The FIFO should be using Gray code for the pointers to prevent data
races between bits when sending the pointers across clock domains.

Both the FIFO and synchronizers need reset logic as well.
libraries/utility/fifo_xclk.vhd [new file with mode: 0644] blob
libraries/utility/xclk_sig.vhd [new file with mode: 0644] blob
libraries/utility/xclk_vec.vhd [new file with mode: 0644] blob
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